RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SAMORI, CARLO
 Distribuzione geografica
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Continente #
NA - Nord America 12.407
EU - Europa 7.791
AS - Asia 4.667
SA - Sud America 1.051
AF - Africa 253
OC - Oceania 12
Continente sconosciuto - Info sul continente non disponibili 8
Totale 26.189
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Nazione #
US - Stati Uniti d'America 12.111
RU - Federazione Russa 2.922
SG - Singapore 1.795
IT - Italia 1.668
CN - Cina 1.279
BR - Brasile 896
VN - Vietnam 660
AT - Austria 488
DE - Germania 455
UA - Ucraina 430
SE - Svezia 306
NL - Olanda 269
GB - Regno Unito 264
FI - Finlandia 252
CA - Canada 225
IE - Irlanda 210
IN - India 177
KR - Corea 149
FR - Francia 146
JP - Giappone 120
MA - Marocco 106
ES - Italia 95
TW - Taiwan 79
JO - Giordania 76
PL - Polonia 71
BE - Belgio 67
HK - Hong Kong 61
AR - Argentina 60
BD - Bangladesh 43
TR - Turchia 42
MX - Messico 41
ZA - Sudafrica 41
EG - Egitto 28
ID - Indonesia 27
CH - Svizzera 26
CI - Costa d'Avorio 25
EC - Ecuador 22
IQ - Iraq 21
GR - Grecia 20
IL - Israele 18
PK - Pakistan 18
VE - Venezuela 18
AL - Albania 16
CO - Colombia 14
PY - Paraguay 13
PT - Portogallo 12
CL - Cile 10
IR - Iran 10
AE - Emirati Arabi Uniti 9
UZ - Uzbekistan 9
AZ - Azerbaigian 8
BG - Bulgaria 8
BJ - Benin 8
CZ - Repubblica Ceca 8
EU - Europa 8
KG - Kirghizistan 8
MO - Macao, regione amministrativa speciale della Cina 8
PE - Perù 8
RO - Romania 8
SA - Arabia Saudita 8
EE - Estonia 7
AU - Australia 6
ET - Etiopia 6
JM - Giamaica 6
KZ - Kazakistan 6
LT - Lituania 6
TN - Tunisia 6
DK - Danimarca 5
MU - Mauritius 5
UY - Uruguay 5
KE - Kenya 4
LA - Repubblica Popolare Democratica del Laos 4
LK - Sri Lanka 4
LV - Lettonia 4
NZ - Nuova Zelanda 4
RS - Serbia 4
TT - Trinidad e Tobago 4
AM - Armenia 3
BB - Barbados 3
BO - Bolivia 3
CR - Costa Rica 3
DZ - Algeria 3
GE - Georgia 3
HU - Ungheria 3
LU - Lussemburgo 3
MK - Macedonia 3
NO - Norvegia 3
PA - Panama 3
PH - Filippine 3
SK - Slovacchia (Repubblica Slovacca) 3
BF - Burkina Faso 2
BY - Bielorussia 2
CV - Capo Verde 2
CY - Cipro 2
DM - Dominica 2
DO - Repubblica Dominicana 2
GA - Gabon 2
GT - Guatemala 2
HN - Honduras 2
HR - Croazia 2
Totale 26.145
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Città #
Ashburn 1.600
Fairfield 1.389
Singapore 1.033
Chandler 930
Woodbridge 798
Wilmington 643
Milan 617
Seattle 585
Houston 584
Cambridge 470
Vienna 467
Santa Clara 439
Moscow 426
Ann Arbor 390
Beijing 287
Hefei 272
Jacksonville 256
Dong Ket 244
Boardman 214
San Jose 211
Dearborn 205
Council Bluffs 190
Los Angeles 188
Dublin 187
Medford 166
Lawrence 160
Kent 122
New York 108
Ottawa 108
San Diego 97
Buffalo 92
Ho Chi Minh City 91
Amsterdam 88
Amman 76
Dallas 74
São Paulo 74
Turin 74
Shanghai 73
Helsinki 71
Frankfurt am Main 70
Seoul 69
Málaga 65
London 63
Tokyo 63
Redwood City 60
Des Moines 58
Kenitra 48
Casablanca 47
Hanoi 47
Munich 45
Chicago 44
Warsaw 39
Montreal 36
Brussels 35
Hong Kong 35
Redmond 35
Stockholm 35
Orem 32
Taipei 32
Turku 29
Denver 28
Brescia 26
Guangzhou 26
Legnano 24
North York 24
Palazzolo sull'Oglio 24
Sesto San Giovanni 24
Washington 24
Abidjan 23
Duncan 23
Rome 23
Belo Horizonte 22
Castilenti 22
Chennai 22
Mountain View 22
Norwalk 22
Toronto 21
Indiana 20
Johannesburg 20
Rio de Janeiro 20
Phoenix 19
Brooklyn 18
Columbus 18
Monza 18
Nanjing 17
Roubaix 17
Zurich 17
Atlanta 16
Cairo 16
Grafing 16
Lappeenranta 16
Redondo Beach 16
Bengaluru 15
The Dalles 15
Wroclaw 15
Chengdu 14
Poplar 14
San Francisco 14
Ankara 13
Falls Church 13
Totale 15.863
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 306
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 257
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 246
Power-jitter trade-off analysis in digital-to-time converters 245
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 238
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 237
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 232
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 231
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 216
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 214
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 211
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 206
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 204
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 201
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 195
A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs 194
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 191
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 190
Bang-bang digital PLLs for wireless systems 190
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 189
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 188
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 183
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 179
Wideband chirp generation techniques in digital phase-locked loops 179
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 176
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 176
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 176
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 175
5-GHz In-Phase Coupled Oscillators with 39% Tuning Range 174
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 174
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 171
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 169
Fast-switching analog PLL with finite-impulse response 167
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 166
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 166
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 166
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 165
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 164
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 163
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 162
A 2.5-GHz DDFS-PLL with 1.8-MHz bandwitdth in 0.35-micron CMOS 161
A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation. 161
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization 161
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 160
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 160
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 159
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 159
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 157
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 156
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 156
Electronic device for generating a fractional frequency 156
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 156
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process 155
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 155
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 155
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 154
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 154
"A Multistandard Σ-Δ Fractional-N Frequency Synthesizer for 802.11a/b/g WLAN" 154
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 153
Noise Analysis and Minimization in Bang-Bang Digital PLLs 152
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 150
A time-digital converter and an electronic system implementing the converter 150
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 150
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 150
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 150
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 150
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 149
A Glitch-Corrector Circuit for Low-Spur ADPLLs 149
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 149
20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power 149
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 148
A spur cancellation technique for MDLL-based frequency synthesizers 148
A multi-tank LC-oscillator 148
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications 148
Low Power RF Digital PLLs with Direct Carrier Modulation 145
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique 144
A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs 144
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 144
Quantization effects in All-Digital Phase-Locked Loops 144
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 144
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 144
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 143
Analysis of power efficiency in high-performance class-B oscillators 142
Simulating phase noise induced from cyclostationary noise sources 141
Concurrent effect of redundancy and switching algorithms in SAR ADCs 140
Integrated Frequency Synthesizers for Wireless Systems 140
An efficient method to compute phase-noise in injection-locked frequency dividers 139
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 138
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 138
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 138
Comparing techniques for spur reduction in digital bang-bang PLLs 138
Convertitore tempo-digitale e sistema elettronico impiegante il convertitore 137
Phase noise and accuracy in quadrature oscillators 137
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band 136
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators 135
A Novel Topology of Coupled Phase-Locked Loops 135
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning 134
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise 133
Reducing flicker noise up-conversion in a 65nm CMOS VCO in the 1.6 to 2.6 GHz band 133
Behavioral Phase-Noise Analysis of Charge-Pump Phase-Locked Loops 133
Totale 16.673
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Categoria #
all - tutte 80.580
article - articoli 35.314
book - libri 448
conference - conferenze 40.533
curatela - curatele 0
other - altro 0
patent - brevetti 2.465
selected - selezionate 0
volume - volumi 1.820
Totale 161.160
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.271 0 0 0 0 0 0 117 167 137 213 111 526
2021/20221.787 63 201 130 98 180 94 97 136 142 117 243 286
2022/20232.305 233 194 68 290 260 258 31 167 377 183 183 61
2023/20241.053 74 191 87 76 62 100 73 51 40 100 32 167
2024/20254.032 41 133 187 89 637 264 187 365 707 241 599 582
2025/20268.706 2.535 2.355 654 1.178 912 715 357 0 0 0 0 0
Totale 26.460