RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SAMORI, CARLO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 8.835
EU - Europa 3.437
AS - Asia 1.001
AF - Africa 27
SA - Sud America 10
Continente sconosciuto - Info sul continente non disponibili 8
OC - Oceania 7
Totale 13.325
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 8.691
IT - Italia 1.188
AT - Austria 464
VN - Vietnam 447
UA - Ucraina 393
SE - Svezia 281
DE - Germania 268
FI - Finlandia 210
CN - Cina 204
IE - Irlanda 177
GB - Regno Unito 158
CA - Canada 143
IN - India 85
ES - Italia 72
JO - Giordania 71
JP - Giappone 70
NL - Olanda 55
BE - Belgio 50
FR - Francia 38
KR - Corea 37
TW - Taiwan 23
HK - Hong Kong 20
CI - Costa d'Avorio 17
GR - Grecia 16
SG - Singapore 15
CH - Svizzera 13
AL - Albania 12
EU - Europa 8
IR - Iran 8
BR - Brasile 7
MO - Macao, regione amministrativa speciale della Cina 6
PL - Polonia 6
RO - Romania 6
MU - Mauritius 5
RU - Federazione Russa 5
TR - Turchia 5
BG - Bulgaria 4
DK - Danimarca 4
NZ - Nuova Zelanda 4
AU - Australia 3
EE - Estonia 3
EG - Egitto 2
HR - Croazia 2
HU - Ungheria 2
ID - Indonesia 2
IL - Israele 2
RS - Serbia 2
SK - Slovacchia (Repubblica Slovacca) 2
AE - Emirati Arabi Uniti 1
AF - Afghanistan, Repubblica islamica di 1
AN - Antille olandesi 1
AR - Argentina 1
CO - Colombia 1
CY - Cipro 1
GE - Georgia 1
KZ - Kazakistan 1
LI - Liechtenstein 1
LK - Sri Lanka 1
LT - Lituania 1
MA - Marocco 1
MK - Macedonia 1
NO - Norvegia 1
PE - Perù 1
PT - Portogallo 1
SC - Seychelles 1
SI - Slovenia 1
ZA - Sudafrica 1
Totale 13.325
Salva come PNG Salva come JPEG
Città #
Fairfield 1.389
Chandler 930
Woodbridge 798
Wilmington 642
Ashburn 636
Seattle 582
Houston 571
Cambridge 470
Vienna 449
Milan 393
Ann Arbor 390
Jacksonville 251
Dong Ket 244
Dearborn 205
Medford 166
Lawrence 160
Dublin 159
Ottawa 101
San Diego 94
Beijing 82
Amman 71
Turin 70
Helsinki 67
Málaga 65
Redwood City 60
Des Moines 53
Shanghai 40
Redmond 35
Tokyo 33
Brussels 32
Amsterdam 30
London 27
New York 25
Legnano 24
North York 24
Washington 24
Duncan 23
Boardman 22
Mountain View 22
Norwalk 22
Indiana 20
Abidjan 17
Columbus 17
Brescia 16
Grafing 16
Los Angeles 16
Rome 14
Falls Church 13
Chicago 12
Auburn Hills 11
Stockholm 11
Edinburgh 10
Hefei 10
Frankfurt am Main 9
Nanjing 9
Pasadena 9
San Jose 9
St Louis 9
Bari 8
Central District 8
San Francisco 8
Hanoi 7
Heverlee 7
Kilburn 7
Lappeenranta 7
Montreal 7
Taipei 7
Zurich 7
Irvine 6
Kunming 6
Princeton 6
Seongnam 6
Shenzhen 6
Taiyuan 6
Basiliano 5
Bengaluru 5
Cork 5
Dallas 5
Fara Gera D'adda 5
Fremont 5
Genoa 5
Goodyear 5
Guangzhou 5
Jinan 5
Lecco 5
Nanchang 5
Naples 5
Neubiberg 5
Pavia 5
Pordenone 5
San Mateo 5
São Paulo 5
Bangalore 4
Copenhagen 4
Cortenuova 4
Groningen 4
Gropello Cairoli 4
Hounslow 4
Izmir 4
Miami 4
Totale 9.940
Salva come PNG Salva come JPEG
Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 206
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 167
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 154
Power-jitter trade-off analysis in digital-to-time converters 153
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 153
Bang-bang digital PLLs for wireless systems 142
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 135
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 131
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 121
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 114
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 114
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 114
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 112
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 112
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 112
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 111
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 111
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 109
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 108
Quantization effects in All-Digital Phase-Locked Loops 107
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 102
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 102
Fast-switching analog PLL with finite-impulse response 101
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 100
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 97
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 97
A multi-tank LC-oscillator 97
Low Power RF Digital PLLs with Direct Carrier Modulation 96
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 95
Electronic device for generating a fractional frequency 95
Wideband chirp generation techniques in digital phase-locked loops 94
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 93
A Circuit Technique Improving the Image Rejection of RF Front-Ends 93
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 92
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 92
Analysis of power efficiency in high-performance class-B oscillators 92
A Dual-Band Frequency Synthesizer for 802.11a/b/g with Fractional-Spur Averaging Technique 91
A spur cancellation technique for MDLL-based frequency synthesizers 91
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 91
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 91
A 2-GHz Low-Power Low-Noise CMOS 32/33 Prescaler 90
Integrated Frequency Synthesizers for Wireless Systems 89
5-GHz In-Phase Coupled Oscillators with 39% Tuning Range 89
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 89
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 89
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 89
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 89
A Glitch-Corrector Circuit for Low-Spur ADPLLs 88
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 88
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 88
AM-to-PM conversion in varactor-tuned oscillators 87
Matching Requirements in LINC Transmitters for OFDM Signals 86
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 86
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 86
Impact of AAC design on phase noise performance of VCOs 85
A time-digital converter and an electronic system implementing the converter 85
Simulating phase noise induced from cyclostationary noise sources 85
Analysis of fractional-n bang-bang digital PLLs using phase switching technique 85
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 85
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 85
Phase Noise and Phase Accuracy in Multiphase LC Oscillators 84
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 84
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 84
Reducing flicker noise up-conversion in a 65nm CMOS VCO in the 1.6 to 2.6 GHz band 84
Noise Analysis and Minimization in Bang-Bang Digital PLLs 84
Fast-switching analog PLL with finite-impulse response 83
A DDS-Based PLL for 2.4-GHz Frequency Synthesis 82
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators 81
A 2.5-GHz DDFS-PLL with 1.8-MHz bandwitdth in 0.35-micron CMOS 80
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band 80
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 80
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 80
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 79
An efficient method to compute phase-noise in injection-locked frequency dividers 78
Low-Power All-Analog Component Separator for an 802.11a/g LINC Transmitter 78
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 78
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling 77
Differential Tuning Oscillators with Reduced Flicker Noise Upconversion 77
A CMOS IF sampling circuit with reduced aliasing for wireless applications 76
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band 76
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing 76
True constant fraction trigger circuit for picosecond photon-timing with ultrafast microchannel-plate photomultipliers 76
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 76
Behavioral Phase-Noise Analysis of Charge-Pump Phase-Locked Loops 76
Phase noise and accuracy in quadrature oscillators 76
Phase noise in digital frequency dividers 75
Convertitore tempo-digitale e sistema elettronico impiegante il convertitore 75
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) 75
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 75
A fully-integrated low-power low-noise 2.6-GHz bipolar VCO for wireless applications 75
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 75
Background adaptive linearization of high-speed digital-to-analog converters 74
A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation. 74
Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling 73
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise 73
Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits 73
Avalanche photodiodes and quenching circuits for single-photon detection 72
A Glitch-Corrector Circuit for Low-Spur ADPLLs 72
Design Issues of LC Tuned Oscillators for Integrated Transceivers 71
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 71
Totale 9.319
Salva come PNG Salva come JPEG
Categoria #
all - tutte 40.523
article - articoli 18.087
book - libri 281
conference - conferenze 19.972
curatela - curatele 0
other - altro 0
patent - brevetti 1.171
selected - selezionate 0
volume - volumi 1.012
Totale 81.046
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019944 0 0 0 0 0 0 0 0 0 0 484 460
2019/20203.144 220 175 78 254 417 417 411 266 348 154 306 98
2020/20212.241 213 134 229 106 203 85 117 167 137 213 111 526
2021/20221.787 63 201 130 98 180 94 97 136 142 117 243 286
2022/20232.305 233 194 68 290 260 258 31 167 377 183 183 61
2023/2024857 74 191 87 76 62 100 73 51 40 100 3 0
Totale 13.526