RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SAMORI, CARLO
 Distribuzione geografica
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Continente #
NA - Nord America 15.586
EU - Europa 8.903
AS - Asia 6.948
SA - Sud America 1.130
AF - Africa 285
OC - Oceania 16
Continente sconosciuto - Info sul continente non disponibili 8
Totale 32.876
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Nazione #
US - Stati Uniti d'America 15.231
RU - Federazione Russa 2.926
IT - Italia 2.438
SG - Singapore 2.059
CN - Cina 1.588
VN - Vietnam 1.035
BR - Brasile 952
HK - Hong Kong 568
AT - Austria 494
DE - Germania 484
KR - Corea 452
UA - Ucraina 434
JP - Giappone 414
FR - Francia 328
SE - Svezia 309
GB - Regno Unito 295
NL - Olanda 290
FI - Finlandia 269
CA - Canada 252
IN - India 218
IE - Irlanda 213
TW - Taiwan 114
MA - Marocco 107
ES - Italia 101
BD - Bangladesh 81
JO - Giordania 79
PL - Polonia 77
BE - Belgio 69
AR - Argentina 66
MX - Messico 55
TR - Turchia 50
ZA - Sudafrica 45
IQ - Iraq 36
EG - Egitto 35
ID - Indonesia 31
CH - Svizzera 30
EC - Ecuador 29
PH - Filippine 29
PK - Pakistan 29
CI - Costa d'Avorio 25
GR - Grecia 22
VE - Venezuela 20
IL - Israele 19
AL - Albania 17
CO - Colombia 17
PT - Portogallo 17
SA - Arabia Saudita 15
CL - Cile 13
PY - Paraguay 13
TH - Thailandia 13
AE - Emirati Arabi Uniti 12
IR - Iran 12
UZ - Uzbekistan 12
MO - Macao, regione amministrativa speciale della Cina 11
AU - Australia 10
AZ - Azerbaigian 10
BG - Bulgaria 10
ET - Etiopia 9
KG - Kirghizistan 9
LT - Lituania 9
PE - Perù 9
RO - Romania 9
BJ - Benin 8
CZ - Repubblica Ceca 8
DZ - Algeria 8
EU - Europa 8
JM - Giamaica 8
TN - Tunisia 8
EE - Estonia 7
KZ - Kazakistan 7
TT - Trinidad e Tobago 7
CR - Costa Rica 6
DK - Danimarca 6
KE - Kenya 6
MU - Mauritius 6
PA - Panama 6
LA - Repubblica Popolare Democratica del Laos 5
LK - Sri Lanka 5
NP - Nepal 5
RS - Serbia 5
UY - Uruguay 5
BO - Bolivia 4
DO - Repubblica Dominicana 4
HR - Croazia 4
HU - Ungheria 4
LB - Libano 4
LV - Lettonia 4
NG - Nigeria 4
NZ - Nuova Zelanda 4
OM - Oman 4
AM - Armenia 3
AO - Angola 3
BA - Bosnia-Erzegovina 3
BB - Barbados 3
GE - Georgia 3
GT - Guatemala 3
LU - Lussemburgo 3
MK - Macedonia 3
NO - Norvegia 3
SC - Seychelles 3
Totale 32.815
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Città #
Ashburn 2.120
Fairfield 1.389
San Jose 1.326
Singapore 1.190
Chandler 934
Milan 877
Woodbridge 799
Wilmington 643
Houston 592
Seattle 587
Hong Kong 484
Vienna 472
Cambridge 470
Santa Clara 469
Moscow 427
Ann Arbor 390
Seoul 360
Los Angeles 340
Tokyo 330
Council Bluffs 313
Beijing 312
The Dalles 277
Hefei 272
Jacksonville 260
Dong Ket 244
Boardman 228
Dearborn 205
Dublin 190
Ho Chi Minh City 185
Lauterbourg 166
Medford 166
Lawrence 160
North Charleston 144
Hanoi 141
New York 137
Dallas 136
Rome 130
Kent 122
Ottawa 108
Amsterdam 101
Turin 100
San Diego 99
Buffalo 96
Shanghai 89
Helsinki 86
Frankfurt am Main 85
São Paulo 79
Amman 78
London 73
Málaga 65
Des Moines 61
Taipei 61
Redwood City 60
Orem 59
Chicago 49
Kenitra 48
Casablanca 47
Munich 45
Warsaw 44
Las Vegas 43
Montreal 43
Guangzhou 42
Stockholm 37
Brussels 35
Redmond 35
Denver 30
Naples 30
Turku 29
Washington 29
Brescia 28
Chennai 28
Salt Lake City 28
Toronto 27
Da Nang 25
North York 25
Phoenix 25
Brooklyn 24
Legnano 24
Monza 24
Norwalk 24
Palazzolo sull'Oglio 24
Sesto San Giovanni 24
Abidjan 23
Belo Horizonte 23
Bologna 23
Duncan 23
Mountain View 23
Castilenti 22
Haiphong 22
Rio de Janeiro 22
Johannesburg 21
Atlanta 20
Cairo 20
Indiana 20
Tianjin 20
Columbus 19
Mumbai 19
Zurich 19
Nanjing 17
Roubaix 17
Totale 20.576
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 368
AM-to-PM conversion in varactor-tuned oscillators 309
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 303
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 293
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 292
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 273
Power-jitter trade-off analysis in digital-to-time converters 272
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 271
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 269
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 266
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 261
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 261
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 254
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 251
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 246
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 245
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 242
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 241
A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs 238
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 237
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 233
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 233
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 224
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 223
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 223
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector 222
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 221
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization 221
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 218
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 218
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning 215
Bang-bang digital PLLs for wireless systems 212
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 211
Wideband chirp generation techniques in digital phase-locked loops 209
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 209
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 206
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 206
Concurrent effect of redundancy and switching algorithms in SAR ADCs 204
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 204
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 204
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 204
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique 203
A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs 203
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 203
5-GHz In-Phase Coupled Oscillators with 39% Tuning Range 202
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 201
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 201
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 200
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 200
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 199
Fast-switching analog PLL with finite-impulse response 197
"A Multistandard Σ-Δ Fractional-N Frequency Synthesizer for 802.11a/b/g WLAN" 197
A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation. 197
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 196
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 195
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 195
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 195
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 193
Electronic device for generating a fractional frequency 193
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 193
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 192
A 2.5-GHz DDFS-PLL with 1.8-MHz bandwitdth in 0.35-micron CMOS 192
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 192
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 191
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 191
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 191
Noise Analysis and Minimization in Bang-Bang Digital PLLs 189
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 188
A Glitch-Corrector Circuit for Low-Spur ADPLLs 187
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 187
A multi-tank LC-oscillator 186
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process 185
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 185
An efficient method to compute phase-noise in injection-locked frequency dividers 185
20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power 185
A time-digital converter and an electronic system implementing the converter 184
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 183
Convertitore tempo-digitale e sistema elettronico impiegante il convertitore 183
A spur cancellation technique for MDLL-based frequency synthesizers 182
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise 179
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 177
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 177
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications 177
Integrated Frequency Synthesizers for Wireless Systems 175
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 175
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 175
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 175
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 175
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion 174
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 174
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 173
A Novel Topology of Coupled Phase-Locked Loops 173
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 173
A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology 171
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 167
Quantization effects in All-Digital Phase-Locked Loops 167
Analysis of power efficiency in high-performance class-B oscillators 167
Low Power RF Digital PLLs with Direct Carrier Modulation 166
Comparing techniques for spur reduction in digital bang-bang PLLs 166
Simulating phase noise induced from cyclostationary noise sources 164
Totale 20.853
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Categoria #
all - tutte 93.775
article - articoli 41.308
book - libri 512
conference - conferenze 46.947
curatela - curatele 0
other - altro 0
patent - brevetti 2.939
selected - selezionate 0
volume - volumi 2.069
Totale 187.550
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021526 0 0 0 0 0 0 0 0 0 0 0 526
2021/20221.787 63 201 130 98 180 94 97 136 142 117 243 286
2022/20232.305 233 194 68 290 260 258 31 167 377 183 183 61
2023/20241.053 74 191 87 76 62 100 73 51 40 100 32 167
2024/20254.032 41 133 187 89 637 264 187 365 707 241 599 582
2025/202615.400 2.535 2.355 654 1.178 912 715 2.702 737 897 1.187 570 958
Totale 33.154