The substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for millimeter-wave frequency bands [1]. To satisfy such stringent requirements, while at the same time guaranteeing fast lock, analog PLLs have been preferred over digital implementations in recent literature [1], [2]. Digital bang-bang PLLs, on the other hand, consume less power and occupy smaller footprint due to the absence of analog loop filters. Digital bang-bang PLLs, however, generally suffer from poor locking performance, which is due to the bang-bang phase detector (BBPD) overloading in presence of large frequency errors, and from increased jitter due to quantization. To improve locking, [3] relies on additional frequency-locking loops (FLLs) to bypass the BBPD when overloaded, at the cost of additional design complexity and power. To improve on quantization noise, [4] proposes a digital PLL based on an enhanced-resolution time-to-digital converter (TDC). However, locking performances were not addressed, and its operation was limited to the integer-N mode. Achieving low-jitter in a fractional-N PLL poses an extra challenge, because of the random jitter introduced by the digital-to-time converter (DTC) and the spectrum folding of the DTC quantization noise arising from its non-linearity and memory effects [1].

A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking

Santiccioli A.;Mercandelli M.;Bertulessi L.;Parisi A.;Lacaita A. L.;Samori C.;Levantino S.
2020

Abstract

The substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for millimeter-wave frequency bands [1]. To satisfy such stringent requirements, while at the same time guaranteeing fast lock, analog PLLs have been preferred over digital implementations in recent literature [1], [2]. Digital bang-bang PLLs, on the other hand, consume less power and occupy smaller footprint due to the absence of analog loop filters. Digital bang-bang PLLs, however, generally suffer from poor locking performance, which is due to the bang-bang phase detector (BBPD) overloading in presence of large frequency errors, and from increased jitter due to quantization. To improve locking, [3] relies on additional frequency-locking loops (FLLs) to bypass the BBPD when overloaded, at the cost of additional design complexity and power. To improve on quantization noise, [4] proposes a digital PLL based on an enhanced-resolution time-to-digital converter (TDC). However, locking performances were not addressed, and its operation was limited to the integer-N mode. Achieving low-jitter in a fractional-N PLL poses an extra challenge, because of the random jitter introduced by the digital-to-time converter (DTC) and the spectrum folding of the DTC quantization noise arising from its non-linearity and memory effects [1].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1141865
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