A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs

This paper presents a complementary (nMOS and pMOS) bootstrapped sampler. The proposed solution is implemented in 28-nm bulk CMOS technology with a 0.9-V supply voltage and integrated with a 250-MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Simulations demonstrate that this topology minimizes on-resistance modulation and charge injection effects, leading to a Total Harmonic Distortion (THD) enhancement of -25-dB at low frequencies and -10-dB at high frequencies compared to the conventional nMOSbased bootstrapped sampler.