Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for frequency synthesizers and clock multipliers because of their simplicity and low power consumption. However, being nonlinear systems, they are proved difficult to analyze and prone to the generation of limit cycles. Under the presence of phase noise originating from the controlled oscillator with 1/f2 and 1/f3 spectral shapes, simple expressions of the output jitter as a function of the loop parameters are developed which allow us to avoid limit cycles and to optimize the design to minimize output jitter.