34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning

The number of high-speed data converters and radio transceivers within the same system-on-chip (SoC) continues to grow, each requiring a dedicated low-noise frequency synthesizer. Digital PLLs (Fig. 34.3.1, top-left) are attractive solutions for low-jitter frequency synthesis, thanks to their ability to scale area and power efficiently with the availability of more advanced CMOS nodes [1]-[8]. The bottleneck in the synthesizer area/power optimization is often represented by the digitally controlled oscillator (DCO), whose flicker-and white-noise-induced phase-noise components contribute to the synthesizer phase noise (Fig. 34.3.1, top-center). In recent years, voltage-biased DCOs have emerged as an attractive alternative to conventional current-biased topologies, eliminating the extra area and noise associated with the biasing networks and achieving a better noise-power compromise by shaping the common-mode (CM) impedance around twice the resonance frequency [9]-[15]. Unfortunately, controlling the CM impedance often requires complex DCO-tuning-bank segmentation and extensive manual resonance tuning [9]-[10], making this approach PVT-sensitive and unsuitable for commercial applications. An automatic CM tuning based on the second-harmonic amplitude [11] and a wideband CM resonance expansion [12], ensuring high CM impedance across the DCO tuning range (TR), have been proposed (Fig. 34.3.1, left). While the first approach operates only in the foreground and requires high sensitivity to second-harmonic amplitude variations, the second one increases the DCO area because of an extra transformer.