This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/ μ s and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.

A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars

Tesolin, Francesco;Dartizio, Simone M.;Castoro, Giacomo;Buccoleri, Francesco;Rossoni, Michele;Cherniak, Dmytro;Samori, Carlo;Lacaita, Andrea L.;Levantino, Salvatore
2024-01-01

Abstract

This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/ μ s and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.
2024
Adaptive filtering
Digital assisted-analog circuits
RF
Radar
CMOS
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1274102
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