This paper describes a 15.6-18.2GHz fractional-N bang-bang digital PLL fabricated in 28nm CMOS. To compensate for the nonlinearity of the digital-to-time converter and reduce the level of fractional spurs, two alternative predistortion techniques are introduced. The adoption of those algorithms operating continuously in background is demonstrated to reduce the level of the in-band fractional spur at 300kHz from -20dBc to -57dBc and -63dBc, respectively. The fabricated PLL achieves FoM of -237.2dB.

A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur

Cherniak, Dmytro;GRIMALDI, LUIGI;BASSI, MATTEO;Samori, Carlo;Levantino, Salvatore
2018

Abstract

This paper describes a 15.6-18.2GHz fractional-N bang-bang digital PLL fabricated in 28nm CMOS. To compensate for the nonlinearity of the digital-to-time converter and reduce the level of fractional spurs, two alternative predistortion techniques are introduced. The adoption of those algorithms operating continuously in background is demonstrated to reduce the level of the in-band fractional spur at 300kHz from -20dBc to -57dBc and -63dBc, respectively. The fabricated PLL achieves FoM of -237.2dB.
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
9781538645451
File in questo prodotto:
File Dimensione Formato  
Cherniak_RFIC2018.pdf

Accesso riservato

Descrizione: Paper
: Publisher’s version
Dimensione 1.83 MB
Formato Adobe PDF
1.83 MB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1065365
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 5
  • ???jsp.display-item.citation.isi??? 3
social impact