This paper describes a 15.6-18.2GHz fractional-N bang-bang digital PLL fabricated in 28nm CMOS. To compensate for the nonlinearity of the digital-to-time converter and reduce the level of fractional spurs, two alternative predistortion techniques are introduced. The adoption of those algorithms operating continuously in background is demonstrated to reduce the level of the in-band fractional spur at 300kHz from -20dBc to -57dBc and -63dBc, respectively. The fabricated PLL achieves FoM of -237.2dB.
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur
Cherniak, Dmytro;GRIMALDI, LUIGI;BASSI, MATTEO;Samori, Carlo;Levantino, Salvatore
2018-01-01
Abstract
This paper describes a 15.6-18.2GHz fractional-N bang-bang digital PLL fabricated in 28nm CMOS. To compensate for the nonlinearity of the digital-to-time converter and reduce the level of fractional spurs, two alternative predistortion techniques are introduced. The adoption of those algorithms operating continuously in background is demonstrated to reduce the level of the in-band fractional spur at 300kHz from -20dBc to -57dBc and -63dBc, respectively. The fabricated PLL achieves FoM of -237.2dB.File in questo prodotto:
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