A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

This article analyzes the jitter-power tradeoff in multiplying delay-locked loops (MDLLs), which differs from the more typical phase-locked loop one, and identifies a design optimization criterion. The methodology is applied to a fractional- ${N}$ MDLL with a sub-sampling bang-bang phase detector and a novel digital-to-time converter (DTC) range-reduction technique, which limits the jitter added to the reference signal, at no additional power penalty. The prototype has been implemented in 65-nm CMOS and covers a 1.6-to-3.0-GHz tuning range, achieving an absolute rms jitter (integrated from 30 kHz to 30 MHz) of 397 fs at 2.5-mW power, with a corresponding jitter-power figure of merit of −244 dB. In-band fractional spurs are as low as −51.5 dB and the occupied core area is 0.0275 mm 2 .