A Glitch-Corrector Circuit for Low-Spur ADPLLs

This paper identifies the unavoidable time skew between counter and TDC inputs, if not properly compensated or corrected, as the major source of spurs in the output spectrum of an All-Digital-Phase-Locked Loops (ADPLLs). The frequency and the level of the main spur induced by the time skew are first analytically estimated. Then, an ADPLL, operating in the 3–4-GHz band, is designed in 90-nm CMOS technology and the reported simulations confirm the theoretical results. A simple glitch- removal circuit, capable of operating even in the presence of fast and large frequency drifts is proposed. The glitch corrector is demonstrated to cancel out the -24-dBc spur and its harmonics, without altering the lock transient behavior of the ADPLL.