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Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops, file e0c31c0d-94de-4599-e053-1705fe0aef77
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1.448
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A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation, file e0c31c0c-4b31-4599-e053-1705fe0aef77
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857
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An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs, file e0c31c0d-4524-4599-e053-1705fe0aef77
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412
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A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop, file e0c31c0e-47f7-4599-e053-1705fe0aef77
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387
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A Digital PLL with Multi-tap LMS-based Bandwidth Control, file e0c31c12-dd1b-4599-e053-1705fe0aef77
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154
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A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity, file e0c31c12-27be-4599-e053-1705fe0aef77
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124
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Introduction to the special issue on the 2014 IEEE international solid-state circuits conferences (ISSCC), file e0c31c0d-517b-4599-e053-1705fe0aef77
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18
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A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping, file e0c31c11-bdec-4599-e053-1705fe0aef77
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8
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Jitter Minimization in Digital PLLs with Mid-Rise TDCs, file e0c31c0f-c8a4-4599-e053-1705fe0aef77
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7
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A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL, file e0c31c0f-c8a5-4599-e053-1705fe0aef77
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7
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A Background Calibration Technique to Control the Bandwidth of Digital PLLs, file e0c31c0c-6b87-4599-e053-1705fe0aef77
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6
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A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop, file e0c31c08-feeb-4599-e053-1705fe0aef77
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5
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PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique, file e0c31c0b-451d-4599-e053-1705fe0aef77
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5
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PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique, file e0c31c0c-2ee5-4599-e053-1705fe0aef77
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5
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A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter, file e0c31c0f-e17e-4599-e053-1705fe0aef77
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5
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A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter, file e0c31c11-f3b5-4599-e053-1705fe0aef77
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5
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A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization, file abc71a39-cb7d-4033-b393-d8f3d61959ff
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4
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A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time, file db11cd2e-cd55-4290-9394-880935980067
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4
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Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops, file e0c31c08-0cef-4599-e053-1705fe0aef77
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4
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A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs, file e0c31c08-2f1c-4599-e053-1705fe0aef77
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4
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A Background Calibration Technique to Control the Bandwidth of Digital PLLs, file e0c31c0c-9543-4599-e053-1705fe0aef77
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4
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A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power, file e0c31c0e-8012-4599-e053-1705fe0aef77
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4
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32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays, file e0c31c10-a067-4599-e053-1705fe0aef77
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4
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A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter, file e0c31c12-7d9f-4599-e053-1705fe0aef77
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4
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Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise, file e0c31c12-991b-4599-e053-1705fe0aef77
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4
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A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion, file e0c31c08-2db5-4599-e053-1705fe0aef77
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3
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AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic, file e0c31c08-3ec8-4599-e053-1705fe0aef77
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3
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Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits, file e0c31c0a-317c-4599-e053-1705fe0aef77
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3
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A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking, file e0c31c0f-e180-4599-e053-1705fe0aef77
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3
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A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking, file e0c31c10-007c-4599-e053-1705fe0aef77
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3
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A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking, file e0c31c10-bae6-4599-e053-1705fe0aef77
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3
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A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters, file 00c77365-1dcb-4f0d-a732-886efb41bd7e
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2
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Concurrent effect of redundancy and switching algorithms in SAR ADCs, file 1089a64e-001b-40d2-8394-318f0dcf4977
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2
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4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology, file 4523210a-27a0-421c-af9b-f29342b35708
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2
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4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering, file 45fbfbe8-b126-4d65-8a02-d11dbd80de63
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2
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A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, file dc36e857-1ff2-4898-8361-0b0ee66b3f1f
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2
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Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion, file e0c31c07-ce7a-4599-e053-1705fe0aef77
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2
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A Wideband 3.6 GHz Digital Delta-Sigma Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation, file e0c31c07-e282-4599-e053-1705fe0aef77
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2
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Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators, file e0c31c07-ed03-4599-e053-1705fe0aef77
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2
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A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration, file e0c31c07-f357-4599-e053-1705fe0aef77
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2
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A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power, file e0c31c08-072d-4599-e053-1705fe0aef77
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2
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A Background calibration technique to control bandwidth in digital PLLs, file e0c31c08-19fa-4599-e053-1705fe0aef77
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2
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An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs, file e0c31c08-1f3d-4599-e053-1705fe0aef77
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2
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General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL, file e0c31c08-29f9-4599-e053-1705fe0aef77
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2
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Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO, file e0c31c08-2ea7-4599-e053-1705fe0aef77
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2
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A 2-GHz Low-Power Low-Noise CMOS 32/33 Prescaler, file e0c31c08-2fc3-4599-e053-1705fe0aef77
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2
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My Two Years in Pavia, file e0c31c08-8579-4599-e053-1705fe0aef77
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2
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Power-jitter trade-off analysis in digital-to-time converters, file e0c31c0a-5693-4599-e053-1705fe0aef77
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2
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A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL, file e0c31c0b-3c65-4599-e053-1705fe0aef77
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2
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Introduction to the special issue on the 2014 IEEE international solid-state circuits conferences (ISSCC), file e0c31c0b-6f86-4599-e053-1705fe0aef77
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2
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Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops, file e0c31c0d-7968-4599-e053-1705fe0aef77
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2
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A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs, file e0c31c10-f770-4599-e053-1705fe0aef77
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2
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A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability, file e0c31c11-6394-4599-e053-1705fe0aef77
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2
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A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs, file e0c31c11-7592-4599-e053-1705fe0aef77
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2
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A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity, file e0c31c12-6cdd-4599-e053-1705fe0aef77
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2
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A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, file e0c31c12-dd20-4599-e053-1705fe0aef77
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2
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A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations, file 0e47c3ec-5efd-49ea-ae15-6591f23d752b
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1
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Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise, file 4b178ef4-db41-4f6d-970d-d982e17d0fd8
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1
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A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping, file 93c4ea14-083d-4128-900f-e6ddf7934922
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1
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Quantization effects in All-Digital Phase-Locked Loops, file e0c31c07-bf9b-4599-e053-1705fe0aef77
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1
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A Circuit Technique Improving the Image Rejection of RF Front-Ends, file e0c31c07-c04b-4599-e053-1705fe0aef77
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1
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Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter, file e0c31c07-c163-4599-e053-1705fe0aef77
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1
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Impact of AAC design on phase noise performance of VCOs, file e0c31c07-c2bd-4599-e053-1705fe0aef77
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1
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AM-to-PM conversion in varactor-tuned oscillators, file e0c31c07-c2f0-4599-e053-1705fe0aef77
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1
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Matching Requirements in LINC Transmitters for OFDM Signals, file e0c31c07-ca53-4599-e053-1705fe0aef77
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1
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A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs, file e0c31c07-cc4f-4599-e053-1705fe0aef77
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1
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Integrated LC oscillators for frequency synthesis in wireless applications, file e0c31c07-cefb-4599-e053-1705fe0aef77
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1
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A fully-integrated low-power low-noise 2.6-GHz bipolar VCO for wireless applications, file e0c31c07-cf8d-4599-e053-1705fe0aef77
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1
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A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop, file e0c31c07-d011-4599-e053-1705fe0aef77
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1
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Multiphase LC Oscillators, file e0c31c07-d3ba-4599-e053-1705fe0aef77
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1
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A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation., file e0c31c07-d3ef-4599-e053-1705fe0aef77
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1
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Tracking capabilities of SPADs for laser ranging., file e0c31c07-d418-4599-e053-1705fe0aef77
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1
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5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS, file e0c31c07-d657-4599-e053-1705fe0aef77
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1
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A DDS-Based PLL for 2.4-GHz Frequency Synthesis, file e0c31c07-d8fc-4599-e053-1705fe0aef77
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1
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Phase noise in digital frequency dividers, file e0c31c07-d9fd-4599-e053-1705fe0aef77
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1
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A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider, file e0c31c07-daf9-4599-e053-1705fe0aef77
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1
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Differentially-Tuned VCO with Reduced Tuning Sensitivity and Flicker Noise Up-Conversion, file e0c31c07-db64-4599-e053-1705fe0aef77
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1
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Fast-switching analog PLL with finite-impulse response, file e0c31c07-db79-4599-e053-1705fe0aef77
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1
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Behavioral Phase-Noise Analysis of Charge-Pump Phase-Locked Loops, file e0c31c07-dcd4-4599-e053-1705fe0aef77
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1
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Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division, file e0c31c07-de91-4599-e053-1705fe0aef77
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1
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Electronic device for generating a fractional frequency, file e0c31c07-dfc2-4599-e053-1705fe0aef77
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1
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Electronic device for generating a fractional frequency, file e0c31c07-dfc3-4599-e053-1705fe0aef77
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1
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A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power, file e0c31c07-e2b0-4599-e053-1705fe0aef77
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1
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Low-Power Divider Retiming in a 3-4GHz Fractional-N PLL, file e0c31c07-e2e2-4599-e053-1705fe0aef77
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1
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A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power, file e0c31c07-e2e3-4599-e053-1705fe0aef77
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1
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Multipath Adaptive Cancellation of Divider Non-Linearity in Fractional-N PLLs, file e0c31c07-e2e4-4599-e053-1705fe0aef77
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1
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Time-to-digital converter with 3-ps resolution and digital linearization algorithm, file e0c31c07-e2e8-4599-e053-1705fe0aef77
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1
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A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation, file e0c31c07-e46d-4599-e053-1705fe0aef77
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1
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A Glitch-Corrector Circuit for Low-Spur ADPLLs, file e0c31c07-ebd9-4599-e053-1705fe0aef77
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1
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20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power, file e0c31c07-ee4d-4599-e053-1705fe0aef77
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1
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Efficient Calculation of the Impulse Sensitivity Function in Oscillators, file e0c31c07-fa55-4599-e053-1705fe0aef77
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1
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Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band, file e0c31c08-0b13-4599-e053-1705fe0aef77
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1
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Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators, file e0c31c08-1054-4599-e053-1705fe0aef77
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1
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A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration, file e0c31c08-10ec-4599-e053-1705fe0aef77
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1
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A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion, file e0c31c08-10ed-4599-e053-1705fe0aef77
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1
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Background adaptive linearization of high-speed digital-to-analog converters, file e0c31c08-10f0-4599-e053-1705fe0aef77
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1
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Simulating phase noise induced from cyclostationary noise sources, file e0c31c08-10f1-4599-e053-1705fe0aef77
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1
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A spur cancellation technique for MDLL-based frequency synthesizers, file e0c31c08-10f2-4599-e053-1705fe0aef77
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1
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Reducing flicker noise up-conversion in a 65nm CMOS VCO in the 1.6 to 2.6 GHz band, file e0c31c08-169b-4599-e053-1705fe0aef77
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1
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A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators, file e0c31c08-17af-4599-e053-1705fe0aef77
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1
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| Totale |
3.601 |