This paper presents a 12-bit successive approx- imation register (SAR)-based time-interleaved (TI) analog-to- digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrations allow reducing the interleaving spurs to less than -73dBc in every configuration. In particular, the proposed difference-based skew calibration efficiently operates in any configuration, not being limited to power-of-2 interleaving factors. Fabricated in a 28-nm bulk CMOS process, the presented TI-ADC achieves a Nyquist- frequency signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 52.01dB and 58.82dBc at 900MS/s, respectively, with an active area occupation of 0.48 mm2 and similar metrics across all the configurations. Featuring a power dissipation of 42.96mW at 900MS/s, the Nyquist-frequency Schreier figure of merit (FoM) is 152.2dB, whereas the Walden one is 146.6fJ/Conv-step.

A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

Be' G.;Bertulessi L.;Ricci L.;Scaletti L.;Mercandelli M.;Lacaita A. L.;Levantino S.;Samori C.;Bonfanti A.
2022

Abstract

This paper presents a 12-bit successive approx- imation register (SAR)-based time-interleaved (TI) analog-to- digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrations allow reducing the interleaving spurs to less than -73dBc in every configuration. In particular, the proposed difference-based skew calibration efficiently operates in any configuration, not being limited to power-of-2 interleaving factors. Fabricated in a 28-nm bulk CMOS process, the presented TI-ADC achieves a Nyquist- frequency signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 52.01dB and 58.82dBc at 900MS/s, respectively, with an active area occupation of 0.48 mm2 and similar metrics across all the configurations. Featuring a power dissipation of 42.96mW at 900MS/s, the Nyquist-frequency Schreier figure of merit (FoM) is 152.2dB, whereas the Walden one is 146.6fJ/Conv-step.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1218501
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