This paper introduces a technique for suppressing the effect of deterministic jitter in phase-locked loops based on multiplying delay-locked loops. A digital loop operating in background of normal operation detects the static phase offset between the two reference-signal paths by means of a single-bit time-to-digital converter and compensates for it by means of a digital-to-time converter.
A spur cancellation technique for MDLL-based frequency synthesizers
MARZIN, GIOVANNI;FENAROLI, ANDREA;MARUCCI, GIOVANNI;LEVANTINO, SALVATORE;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2013-01-01
Abstract
This paper introduces a technique for suppressing the effect of deterministic jitter in phase-locked loops based on multiplying delay-locked loops. A digital loop operating in background of normal operation detects the static phase offset between the two reference-signal paths by means of a single-bit time-to-digital converter and compensates for it by means of a digital-to-time converter.File in questo prodotto:
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