A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization

This paper presents a linearity enhancement method, named charge linearization technique (CLT), for top-plate input successive approximation register (SAR) data converters. The proposed CLT removes the linearity degradation due to the non-linear parasitic capacitance of the comparator. Consequently, the constraint on the size of the comparator is relieved. An 11-bit redundant SAR converter featuring the proposed linearization method has been designed and fabricated in a 28-nm CMOS process. The converter achieves a 61.3-dB signal-to-noise-and-distortion ratio (SNDR) and 80.7-dB spurious-free dynamic range (SFDR) while running at 250 MS/s and consuming 5.04 mW from a 0.9-V supply. The aforementioned techniquse enhances the SNDR and SFDR by up to 2.5 dB and 17.4 dB, respectively.