This paper presents an analysis of power efficiency in LC voltage-controlled oscillators (VCOs). Three different class-B topologies are compared under different operating conditions, demonstrating that the CMOS oscillator embedding two tail resonators achieves the best power efficiency and, consequently, best phase-noise-versus-power trade-off. A 65-nm CMOS prototype in post-layout simulations achieves a phase noise of -159 dBc/Hz at 20-MHz offset from the 3.6-GHz carrier, while dissipating 4.5 mW from 1.2-V power supply and covering 21.8% tuning range.

Analysis of power efficiency in high-performance class-B oscillators

BERTULESSI, LUCA;LEVANTINO, SALVATORE;SAMORI, CARLO
2016

Abstract

This paper presents an analysis of power efficiency in LC voltage-controlled oscillators (VCOs). Three different class-B topologies are compared under different operating conditions, demonstrating that the CMOS oscillator embedding two tail resonators achieves the best power efficiency and, consequently, best phase-noise-versus-power trade-off. A 65-nm CMOS prototype in post-layout simulations achieves a phase noise of -159 dBc/Hz at 20-MHz offset from the 3.6-GHz carrier, while dissipating 4.5 mW from 1.2-V power supply and covering 21.8% tuning range.
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
978-1-5090-0493-5
978-1-5090-0493-5
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1001837
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