The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-to-time-converter (DTC) has become ubiquitous to meet performance targets, as it greatly improves integrated jitter by re-aligning the edges of the reference and the divider signals (top-left of Fig. 4.5.1) [2], [2]. Unfortunately, any DTC non-linearity converts the quantization error (QE) , driving the DTC into fractional spurs in the PLL spectrum, thus degrading the integrated jitter. Several digital techniques have been proposed to reduce the DTC non-linearity either at the cost of increasing hardware resources [3] or requiring calibration loops with long convergence times [4]. Other techniques dither the DTC control word [5], [6], spreading the spurious-tones power over a larger bandwidth, but the total jitter improvement is limited. This work introduces a fractional-spur-cancellation technique based on a multi-DTC topology with phase-shifted quantization-error sequences that allows the cancellation of the dominant fractional-spur tones and, at the same time, the reduction of the in-band phase-noise (PN). The concept is demonstrated in a 9.25GHz fractional-N DPLL, which achieves a total rms jitter of 77.1fs (including fractional spurs) for near-integer channels and an in-band fractional spur of −60.3dBc.

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Castoro, Giacomo;Dartizio, Simone M.;Tesolin, Francesco;Buccoleri, Francesco;Rossoni, Michele;Cherniak, Dmytro;Bertulessi, Luca;Samori, Carlo;Lacaita, Andrea L.;Levantino, Salvatore
2023-01-01

Abstract

The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-to-time-converter (DTC) has become ubiquitous to meet performance targets, as it greatly improves integrated jitter by re-aligning the edges of the reference and the divider signals (top-left of Fig. 4.5.1) [2], [2]. Unfortunately, any DTC non-linearity converts the quantization error (QE) , driving the DTC into fractional spurs in the PLL spectrum, thus degrading the integrated jitter. Several digital techniques have been proposed to reduce the DTC non-linearity either at the cost of increasing hardware resources [3] or requiring calibration loops with long convergence times [4]. Other techniques dither the DTC control word [5], [6], spreading the spurious-tones power over a larger bandwidth, but the total jitter improvement is limited. This work introduces a fractional-spur-cancellation technique based on a multi-DTC topology with phase-shifted quantization-error sequences that allows the cancellation of the dominant fractional-spur tones and, at the same time, the reduction of the in-band phase-noise (PN). The concept is demonstrated in a 9.25GHz fractional-N DPLL, which achieves a total rms jitter of 77.1fs (including fractional spurs) for near-integer channels and an in-band fractional spur of −60.3dBc.
2023
2023 IEEE International Solid- State Circuits Conference (ISSCC)
978-1-6654-9016-0
CMOS
Frequency synthesis
PLL
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1233464
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