A ΔΣ fractional-N digital PLL combining a single-bit TDC and a 10b feedback controllable delay achieves RMS jitter (3kHz to 30MHz) lower than 560fsrms over the 2.92-to-4.05GHz range, even in the worst-case of fractional spur falling within the PLL bandwidth. The 40MHz reference spur is below -72dBc. The power dissipation is 4.5mW and the core area is 0.22aqmm in 65nm CMOS.
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power
MARZIN, GIOVANNI;LEVANTINO, SALVATORE;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2011-01-01
Abstract
A ΔΣ fractional-N digital PLL combining a single-bit TDC and a 10b feedback controllable delay achieves RMS jitter (3kHz to 30MHz) lower than 560fsrms over the 2.92-to-4.05GHz range, even in the worst-case of fractional spur falling within the PLL bandwidth. The 40MHz reference spur is below -72dBc. The power dissipation is 4.5mW and the core area is 0.22aqmm in 65nm CMOS.File in questo prodotto:
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