Local oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier frequencies. Analog PLLs demonstrated to have successfully met the required performance levels with integer-N [1] and fractional-N frequency synthesis [2], while involving large analog filters that are not amenable to down scaling in nanoscale CMOS processes. By contrast, digital PLLs are compact and scalable, but suffer from quantization noise of time-to-digital converters (TDCs), which adds up to thermal noise [3]. A viable solution to achieve both compactness and very low jitter is to employ an analog type-I PLL with a sampling phase detector (SPD) [4]. Unfortunately, the limited range of the SPD, combined with the tuning-dependent phase error, typical of a type-I PLL, which further reduces the available SPD range, produces a narrow PLL locking range and confines the architecture to integer-N frequency synthesis. This work presents a 12.5GHz fractional-N type-I sampling PLL achieving an rms jitter of 58.2fs (integrated from 1kHz to 100MHz) at 18mW power consumption and occupying an area of 0.16mm2. A 1b TDC with a simple digital phase-error-correction (DPEC) circuit is leveraged to simultaneously (i) limit the SPD phase error with no extra quantization noise and (ii) extract a digitized version of the phase error needed for the accurate cancellation of the fractional quantization error.

A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter

Mercandelli M.;Santiccioli A.;Parisi A.;Bertulessi L.;Lacaita A. L.;Samori C.;Levantino S.
2020

Abstract

Local oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier frequencies. Analog PLLs demonstrated to have successfully met the required performance levels with integer-N [1] and fractional-N frequency synthesis [2], while involving large analog filters that are not amenable to down scaling in nanoscale CMOS processes. By contrast, digital PLLs are compact and scalable, but suffer from quantization noise of time-to-digital converters (TDCs), which adds up to thermal noise [3]. A viable solution to achieve both compactness and very low jitter is to employ an analog type-I PLL with a sampling phase detector (SPD) [4]. Unfortunately, the limited range of the SPD, combined with the tuning-dependent phase error, typical of a type-I PLL, which further reduces the available SPD range, produces a narrow PLL locking range and confines the architecture to integer-N frequency synthesis. This work presents a 12.5GHz fractional-N type-I sampling PLL achieving an rms jitter of 58.2fs (integrated from 1kHz to 100MHz) at 18mW power consumption and occupying an area of 0.16mm2. A 1b TDC with a simple digital phase-error-correction (DPEC) circuit is leveraged to simultaneously (i) limit the SPD phase error with no extra quantization noise and (ii) extract a digitized version of the phase error needed for the accurate cancellation of the fractional quantization error.
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
978-1-7281-3205-1
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1141864
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