Time-to-digital converter with 3-ps resolution and digital linearization algorithm

This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC with an equivalent number of samples equal to N2, at the negligible area cost of doubling the number of minimum load capacitors. The concept is proved in a 65-nm CMOS technology 40MHz TDC, which achieves a 3ps resolution. The differential nonlinearity is reduced from 1LSB to less than 0.2LSB.