Sub-100fs fractional-N PLLs in the tens of GHz range are required by modern wireless standards such as 5G [1]. The main factors limiting jitter and spot-noise in a digital PLL (DPLL) are on one hand the phase noise of the digitally controlled oscillator (DCO) and, on the other hand, the quantization noise (QN) introduced by the DCO frequency granularity. Though several approaches, such as multi-core oscillators [2], [3] or multi-core PLLs [4] have been explored to trade power consumption against phase noise, the theoretical phase-noise reduction of 3dB per each doubling of the number of cores is never fully obtained in practice. The second issue of the QN introduced at the DCO analog/digital domain crossing could be in principle solved by increasing DCO resolution, but this comes at the cost of a larger number of DCO bits which entails higher design complexity and larger area occupation. Alternatively, a $\Delta\Sigma$ modulator driving the DCO can be used to high-pass-shape the QN and its clock oversampled with respect to the reference frequency to move the QN bump in the spectrum to higher frequency. Prior solutions to generate the $\Delta\Sigma$ clock are based either on an auxiliary PLL which multiplies the reference clock frequency or a high-speed frequency divider that divides the DCO output [3]. While in the first case pulling phenomena between auxiliary and main PLL are observed to worsen performance, in the second case, the frequency divider may consume large power and metastability in the crossing between the two non-synchronous clock domains has to be addressed. This work presents a 9GHz fractional-N digital bang-bang PLL (BBPLL) achieving 72fs rms total integrated jitter (including spurs) at near-integer channels and -140.7dBc/Hz spot phase-noise level at 10MHz offset. The PLL relies on a low-power quadrupler calibrated by a background digital-period-averaging (DPA) algorithm to reduce the QN of the $\Delta\Sigma$ DCO, and on a low-noise true-in-phase combiner (TIPC) which combines two PLL cores to reduce phase noise.

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler

Buccoleri F.;Dartizio S. M.;Tesolin F.;Santiccioli A.;Bevilacqua A.;Bertulessi L.;Cherniak D.;Samori C.;Lacaita A. L.;Levantino S.
2022

Abstract

Sub-100fs fractional-N PLLs in the tens of GHz range are required by modern wireless standards such as 5G [1]. The main factors limiting jitter and spot-noise in a digital PLL (DPLL) are on one hand the phase noise of the digitally controlled oscillator (DCO) and, on the other hand, the quantization noise (QN) introduced by the DCO frequency granularity. Though several approaches, such as multi-core oscillators [2], [3] or multi-core PLLs [4] have been explored to trade power consumption against phase noise, the theoretical phase-noise reduction of 3dB per each doubling of the number of cores is never fully obtained in practice. The second issue of the QN introduced at the DCO analog/digital domain crossing could be in principle solved by increasing DCO resolution, but this comes at the cost of a larger number of DCO bits which entails higher design complexity and larger area occupation. Alternatively, a $\Delta\Sigma$ modulator driving the DCO can be used to high-pass-shape the QN and its clock oversampled with respect to the reference frequency to move the QN bump in the spectrum to higher frequency. Prior solutions to generate the $\Delta\Sigma$ clock are based either on an auxiliary PLL which multiplies the reference clock frequency or a high-speed frequency divider that divides the DCO output [3]. While in the first case pulling phenomena between auxiliary and main PLL are observed to worsen performance, in the second case, the frequency divider may consume large power and metastability in the crossing between the two non-synchronous clock domains has to be addressed. This work presents a 9GHz fractional-N digital bang-bang PLL (BBPLL) achieving 72fs rms total integrated jitter (including spurs) at near-integer channels and -140.7dBc/Hz spot phase-noise level at 10MHz offset. The PLL relies on a low-power quadrupler calibrated by a background digital-period-averaging (DPA) algorithm to reduce the QN of the $\Delta\Sigma$ DCO, and on a low-noise true-in-phase combiner (TIPC) which combines two PLL cores to reduce phase noise.
Proceedings of the Custom Integrated Circuits Conference
978-1-6654-0756-4
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1218504
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