Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N frequency synthesizers in the sub-6GHz range, but, when used in the mm-wave range, at 30GHz and above, they typically feature poor jitter-power trade-off. This paper presents a 30GHz fractional-N DPLL in 65nm low-power (LP) CMOS achieving 198fs integrated jitter at 35mW power. The DPLL based on a digital-to-time converter (DTC) combines: (i) sub-sampling bang-bang phase detection to reduce power consumption, (ii) a digital error correction to reduce DTC noise contribution, and (iii) a low-power wide-lock-range divide-by-six circuit to allow operation up to 34GHz.

16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS

Grimaldi, Luigi;Bertulessi, Luca;Karman, Saleh;Samori, Carlo;Lacaita, Andrea L.;Levantino, Salvatore
2019

Abstract

Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N frequency synthesizers in the sub-6GHz range, but, when used in the mm-wave range, at 30GHz and above, they typically feature poor jitter-power trade-off. This paper presents a 30GHz fractional-N DPLL in 65nm low-power (LP) CMOS achieving 198fs integrated jitter at 35mW power. The DPLL based on a digital-to-time converter (DTC) combines: (i) sub-sampling bang-bang phase detection to reduce power consumption, (ii) a digital error correction to reduce DTC noise contribution, and (iii) a low-power wide-lock-range divide-by-six circuit to allow operation up to 34GHz.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
9781538685310
Electronic, Optical and Magnetic Materials; Electrical and Electronic Engineering
CMOS
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1081171
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