This work presents a fractional- N digital PLL leveraging a digital-to-time converter (DTC) chopping technique to improve spectral purity and jitter. By randomly moving the DTC between the reference and divider paths of the PLL, the fractional spurs induced by DTC non-linearity and the DTC flicker noise are suppressed. The synthesizer, fabricated in 28nm CMOS, achieves 79.3fs rms jitter and -63.6dBc fractional spur at 9.275GHz near-integer channels.
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
Moleri, Riccardo;Dartizio, Simone Mattia;Rossoni, Michele;Castoro, Giacomo;Tesolin, Francesco;Cherniak, Dmytro;Samori, Carlo;Lacaita, Andrea Leonardo;Levantino, Salvatore
2024-01-01
Abstract
This work presents a fractional- N digital PLL leveraging a digital-to-time converter (DTC) chopping technique to improve spectral purity and jitter. By randomly moving the DTC between the reference and divider paths of the PLL, the fractional spurs induced by DTC non-linearity and the DTC flicker noise are suppressed. The synthesizer, fabricated in 28nm CMOS, achieves 79.3fs rms jitter and -63.6dBc fractional spur at 9.275GHz near-integer channels.File in questo prodotto:
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