This paper proposes a method for speeding up the linear settling response of integer-N PLL's. Extending the discrete-time model of the PLL, simple design rules are derived which guarantee accurate frequency settling in few reference cycles. Simulations show that the proposed technique can improve the settling time of a conventional PLL by about 10 times. A 2.5-GHz frequency synthesizer with 1-MHz reference is designed according to the proposed technique in an existing 0.35 μm-CMOS technology. A 60-MHz frequency step within 0.1-ppm accuracy is performed in 15 μs. The simulated reference spur is -60 dBc.

Fast-switching analog PLL with finite-impulse response

LEVANTINO, SALVATORE;ROMANO', LUCA;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2004

Abstract

This paper proposes a method for speeding up the linear settling response of integer-N PLL's. Extending the discrete-time model of the PLL, simple design rules are derived which guarantee accurate frequency settling in few reference cycles. Simulations show that the proposed technique can improve the settling time of a conventional PLL by about 10 times. A 2.5-GHz frequency synthesizer with 1-MHz reference is designed according to the proposed technique in an existing 0.35 μm-CMOS technology. A 60-MHz frequency step within 0.1-ppm accuracy is performed in 15 μs. The simulated reference spur is -60 dBc.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04
9780780382510
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/271894
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