The advent of the next-generation wireless communication standards demands increasingly faster transceivers, posing extremely challenging requirements on the frequency-synthesizer integrated jitter [1, 2]. As demonstrated in [1], the bang-bang digital-PLL (DPLL) architecture can meet the required jitter performance while synthesizing fractional-N frequencies, and it is highly attractive for its reduced power consumption, compact footprint, and straightforward integration in modern scaled CMOS technologies. However, due to the intrinsic bang-bang phase-detector (BBPD) quantization noise, analog PLLs still achieve superior performance in terms of the jitter-power product [2]. To overcome the BBPD quantization noise in DPLLs, [3] relies on an 8b ADC to digitize the PLL phase error with a physical resolution below the input-jitter, leading to increased design complexity, with an area and power penalty. The first attempt to reduce the quantization noise of a 1b TDC was done in [4] by implementing a charge-pump-based DeltaSigma TDC in a fractional-N DPLL. Unfortunately, the large delay introduced in the delta modulation path has so far hindered its adoption in low-jitter DPLLs. This work presents a 13GHz fractional-N DPLL achieving 79. 5fs random jitter and 107.6fs jitter including spurs in near-integer channels. The DPLL is based on a BBPD with (i) quantization noise shaping with a fine and tunable delta modulation, and (ii) a digital background adaptive-shaping-control technique to optimally reduce the BBPD quantization.

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter

Mercandelli M.;Santiccioli A.;Dartizio S. M.;Shehata A.;Tesolin F.;Karman S.;Bertulessi L.;Buccoleri F.;Parisi A.;Lacaita A. L.;Samori C.;Levantino S.
2021

Abstract

The advent of the next-generation wireless communication standards demands increasingly faster transceivers, posing extremely challenging requirements on the frequency-synthesizer integrated jitter [1, 2]. As demonstrated in [1], the bang-bang digital-PLL (DPLL) architecture can meet the required jitter performance while synthesizing fractional-N frequencies, and it is highly attractive for its reduced power consumption, compact footprint, and straightforward integration in modern scaled CMOS technologies. However, due to the intrinsic bang-bang phase-detector (BBPD) quantization noise, analog PLLs still achieve superior performance in terms of the jitter-power product [2]. To overcome the BBPD quantization noise in DPLLs, [3] relies on an 8b ADC to digitize the PLL phase error with a physical resolution below the input-jitter, leading to increased design complexity, with an area and power penalty. The first attempt to reduce the quantization noise of a 1b TDC was done in [4] by implementing a charge-pump-based DeltaSigma TDC in a fractional-N DPLL. Unfortunately, the large delay introduced in the delta modulation path has so far hindered its adoption in low-jitter DPLLs. This work presents a 13GHz fractional-N DPLL achieving 79. 5fs random jitter and 107.6fs jitter including spurs in near-integer channels. The DPLL is based on a BBPD with (i) quantization noise shaping with a fine and tunable delta modulation, and (ii) a digital background adaptive-shaping-control technique to optimally reduce the BBPD quantization.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
978-1-7281-9549-0
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1166753
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