This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path analog loop filter, the impact of charge-pump noise on PLL phase noise is reduced to negligible levels with no penalty on power dissipation. Additionally, the proposed topology enables an efficient cancella- tion of the ΔΣ quantization error, a novel scheme for the calibration of the loop filter parameters and a low-sensitivity VCO, which is beneficial in lowering the reference-spur level. The 3.0-to-4.0-GHz fractional-N synthesizer integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat phase noise is −105 dBc/Hz over the 5.5-MHz PLL bandwidth with a 40-MHz crystal reference.

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration

LEVANTINO, SALVATORE;MARZIN, GIOVANNI;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2013-01-01

Abstract

This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path analog loop filter, the impact of charge-pump noise on PLL phase noise is reduced to negligible levels with no penalty on power dissipation. Additionally, the proposed topology enables an efficient cancella- tion of the ΔΣ quantization error, a novel scheme for the calibration of the loop filter parameters and a low-sensitivity VCO, which is beneficial in lowering the reference-spur level. The 3.0-to-4.0-GHz fractional-N synthesizer integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat phase noise is −105 dBc/Hz over the 5.5-MHz PLL bandwidth with a 40-MHz crystal reference.
2013
sezele; CMOS; Frequency synthesiser; phase-locked loops (PLLs); Phase noise
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/743167
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