The adoption of digital-to-time converters (DTCs) along with coarse, or even single-bit, time-to-digital converters (TDCs) is known to substantially reduce jitter and power consumption of digital fractional-N PLLs. Beside these advantages, DTC-based PLLs enable an adaptive pre-distortion algorithm which mitigates the nonlinearity of the DTC and the nonlinearity-induced fractional spurs. This paper provides a novel analytical framework of this linearization algorithm and demonstrates a reduction of fractional-N in-band spurs by 25 dB in a 3.6-GHz digital PLL.

Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs

LEVANTINO, SALVATORE;GRIMALDI, LUIGI;SAMORI, CARLO
2016

Abstract

The adoption of digital-to-time converters (DTCs) along with coarse, or even single-bit, time-to-digital converters (TDCs) is known to substantially reduce jitter and power consumption of digital fractional-N PLLs. Beside these advantages, DTC-based PLLs enable an adaptive pre-distortion algorithm which mitigates the nonlinearity of the DTC and the nonlinearity-induced fractional spurs. This paper provides a novel analytical framework of this linearization algorithm and demonstrates a reduction of fractional-N in-band spurs by 25 dB in a 3.6-GHz digital PLL.
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
978-1-5090-0493-5
978-1-5090-0493-5
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1001840
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