A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs

This paper presents an ultra-low-power differential Ring Amplifier (RA) that exploits Floating Inverter Amplifiers (FIAs) as building blocks to derive an autozeroing-free, area- and energy-efficient topology. The proposed solution is implemented in a 28-nm bulk CMOS technology with a 0.9-V supply voltage and is used as a residue amplifier for a 500-MS/s Pipeline Successive Approximation Register (SAR) analog-to-digital converter (ADC). Simulations show that the amplifier settles within 500 ps and achieves an input-referred noise of 169 μV with a power consumption of only 190 μW. These numbers result in a Figureof- Merit (FoM) of 10.9 nJ·(μV)^2, which favorably compares with the state-of-the-art.