SAMORI, CARLO

SAMORI, CARLO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 185 (tempo di esecuzione: 0.086 secondi).
Titolo Data di pubblicazione Autori File
"A Multistandard Σ-Δ Fractional-N Frequency Synthesizer for 802.11a/b/g WLAN" 1-gen-2007 BONFANTI, ANDREA GIOVANNISAMORI, CARLOLACAITA, ANDREA LEONARDO
"Integrated wireless transceivers design with emphasis on IF sampling". 1-gen-1999 SAMORI, CARLO +
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 1-gen-2003 SAMORI, CARLOLEVANTINO, SALVATORELACAITA, ANDREA LEONARDO +
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 1-gen-2019 Grimaldi, LuigiBertulessi, LucaKarman, SalehSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power 1-gen-2012 MARZIN, GIOVANNILEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
5-GHz In-Phase Coupled Oscillators with 39% Tuning Range 1-gen-2004 SAMORI, CARLOPOLITI, MARCO +
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 1-gen-2006 BONFANTI, ANDREA GIOVANNILEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications 1-gen-2001 SAMORI, CARLOLEVANTINO, SALVATORE +
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli, AlessioMercandelli, MarioLacaita, Andrea L.Samori, CarloLevantino, Salvatore
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli A.Mercandelli M.Lacaita A. L.Samori C.Levantino S.
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 1-gen-2015 LEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 1-gen-2014 MARUCCI, GIOVANNIFENAROLI, ANDREALEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 1-gen-2022 Lorenzo ScalettiGabriele BeAngelo ParisiLuca BertulessiLuca RicciMario MercandelliSalvatore LevantinoCarlo SamoriAndrea Bonfanti
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2022 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 1-gen-2020 Mercandelli M.Santiccioli A.Parisi A.Bertulessi L.Lacaita A. L.Samori C.Levantino S. +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +