BB digital PLLs, thanks to the use of a single-bit TDC, i.e. a BBPD, dissipate much less power than their counterparts employing a multi-bit TDC. The main issues related to the adoption of such a hard nonlinearity in the loop, i.e. how to avoid limit cycles in fractional-mode so as to obtain a wireless-class output spectrum, how to control the bandwidth, and how to guarantee a fast lock, have been discussed. We have shown that digitally intensive architectures enable powerful calibration circuits, mostly based on LMS techniques, to solve these issues, even in the presence of PVT variations.

Bang-bang digital PLLs for wireless systems

S. Levantino;c. Samori
2020-01-01

Abstract

BB digital PLLs, thanks to the use of a single-bit TDC, i.e. a BBPD, dissipate much less power than their counterparts employing a multi-bit TDC. The main issues related to the adoption of such a hard nonlinearity in the loop, i.e. how to avoid limit cycles in fractional-mode so as to obtain a wireless-class output spectrum, how to control the bandwidth, and how to guarantee a fast lock, have been discussed. We have shown that digitally intensive architectures enable powerful calibration circuits, mostly based on LMS techniques, to solve these issues, even in the presence of PVT variations.
2020
Phase-Locked Frequency Generation and Clocking
978-1-78561-885-7
978-1-78561-886-4
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1142468
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