Digital-to-time converters are one of the main building blocks in time-domain signal processing. The jitter-power product is analysed and shown to scale up linearly as the full-scale delay range in current-mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current-mode ones only when their output range is lower than about 1.4 times the clock period.

Power-jitter trade-off analysis in digital-to-time converters

SANTICCIOLI, ALESSIO;SAMORI, CARLO;LACAITA, ANDREA LEONARDO;LEVANTINO, SALVATORE
2017

Abstract

Digital-to-time converters are one of the main building blocks in time-domain signal processing. The jitter-power product is analysed and shown to scale up linearly as the full-scale delay range in current-mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current-mode ones only when their output range is lower than about 1.4 times the clock period.
sezele, CMOS, timing circuits
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1027274
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