In this work, a 12-bit, 150-MS/s, 13-steps redundant asynchronous SAR ADC achieving better than 63-dB SNDR and 72-dB SFDR with a 100-MHz Equivalent Resolution Bandwidth (ERBW) is presented. To achieve a high conversion rate without impairing accuracy, the implemented ADC features a custom sub-fF unit capacitance with mismatch calibration in the digital domain, a sub-radix-2 CDAC which introduces redundancy in the conversion, and a new version of the monotonic switching algorithm. The proposed switching procedure halves the common-mode voltage variation at the input of the comparator without requiring any additional voltage reference and without increasing the SAR logic complexity. The presented SAR ADC is fabricated in a 28-nm bulk CMOS process as part of a 6x time-interleaved converter.

A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters

Lorenzo Scaletti;Gabriele Be;Angelo Parisi;Luca Bertulessi;Luca Ricci;Mario Mercandelli;Salvatore Levantino;Carlo Samori;Andrea Bonfanti
2022-01-01

Abstract

In this work, a 12-bit, 150-MS/s, 13-steps redundant asynchronous SAR ADC achieving better than 63-dB SNDR and 72-dB SFDR with a 100-MHz Equivalent Resolution Bandwidth (ERBW) is presented. To achieve a high conversion rate without impairing accuracy, the implemented ADC features a custom sub-fF unit capacitance with mismatch calibration in the digital domain, a sub-radix-2 CDAC which introduces redundancy in the conversion, and a new version of the monotonic switching algorithm. The proposed switching procedure halves the common-mode voltage variation at the input of the comparator without requiring any additional voltage reference and without increasing the SAR logic complexity. The presented SAR ADC is fabricated in a 28-nm bulk CMOS process as part of a 6x time-interleaved converter.
2022
Northeast Workshop on Circuits and Systems (NEWCAS): 2022 20TH IEEE INTERREGIONAL NEWCAS CONFERENCE (NEWCAS)
978-1-6654-0105-0
SAR
analog to digital
monotonic switching
redundancy
CMOS
data converter
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1220934
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