Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f^2 and 1/^3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.

Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

MARUCCI, GIOVANNI;LEVANTINO, SALVATORE;MAFFEZZONI, PAOLO;SAMORI, CARLO
2014

Abstract

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f^2 and 1/^3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.
File in questo prodotto:
File Dimensione Formato  
TCASI_Marucci_Jan_2014.pdf

Accesso riservato

: Publisher’s version
Dimensione 2.24 MB
Formato Adobe PDF
2.24 MB Adobe PDF   Visualizza/Apri
Analysis and Design of Low-Jitter Digital Bang-Bang éhase-Locked Loops_11311-733573_Levantino.pdf

accesso aperto

: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 1.95 MB
Formato Adobe PDF
1.95 MB Adobe PDF Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/733573
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 41
  • ???jsp.display-item.citation.isi??? 33
social impact