This paper presents a technique to regulate the bandwidth of digital phase-locked loops (PLLs), where a fully digital automatic control circuit, running in background, is used to desensitize loop gain from analog parameters. The method that is based on an adaptive least-mean-squares algorithm requires no injection of a training sequence, potentially degrading phase noise performance, and is suitable in particular for bang-bang PLLs, where the bandwidth depends on the input noise. The operating principle is first introduced and discussed with the help of an intuitive time-domain model, and the algorithm extension addressing the practical implementation issues associated with loop latency is then presented. The calibration circuit is embedded in a 65-nm CMOS digital PLL that achieves 400-fs integrated rms jitter with a power consumption of 4.5 mW. The algorithm enables digital programmability of loop bandwidth from 100 kHz to 2 MHz with an error below 1 dB between the theoretical and measured PLL noise transfer functions.

A Background Calibration Technique to Control the Bandwidth of Digital PLLs

MERCANDELLI, MARIO;Luigi Grimaldi;Luca Bertulessi;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino
2018

Abstract

This paper presents a technique to regulate the bandwidth of digital phase-locked loops (PLLs), where a fully digital automatic control circuit, running in background, is used to desensitize loop gain from analog parameters. The method that is based on an adaptive least-mean-squares algorithm requires no injection of a training sequence, potentially degrading phase noise performance, and is suitable in particular for bang-bang PLLs, where the bandwidth depends on the input noise. The operating principle is first introduced and discussed with the help of an intuitive time-domain model, and the algorithm extension addressing the practical implementation issues associated with loop latency is then presented. The calibration circuit is embedded in a 65-nm CMOS digital PLL that achieves 400-fs integrated rms jitter with a power consumption of 4.5 mW. The algorithm enables digital programmability of loop bandwidth from 100 kHz to 2 MHz with an error below 1 dB between the theoretical and measured PLL noise transfer functions.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1066543
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