This paper presents a 14GHz digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change in one sample of a 200MHz clock. The architecture is based on a fractional-N bang-bang digital PLL exploiting an adaptive DCO-tuning requantizer, which mitigates the segmentation-induced nonlinearity of the DCO, and a novel deskewing circuit, which improves the EVM at high bit rates. The modulation error, expressed in terms of RMS value of the EVM, is below -42dB for a 250Mb/s 32-PSK modulated carrier. The phase modulator, integrated in a 28nm CMOS process, consumes 31.5mW power, achieving 0.13nJ/bit energy consumption.

A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL

Mercandelli, Mario;Bertulessi, Luca;Santiccioli, Alessio;Samori, Carlo;Levantino, Salvatore
2020

Abstract

This paper presents a 14GHz digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change in one sample of a 200MHz clock. The architecture is based on a fractional-N bang-bang digital PLL exploiting an adaptive DCO-tuning requantizer, which mitigates the segmentation-induced nonlinearity of the DCO, and a novel deskewing circuit, which improves the EVM at high bit rates. The modulation error, expressed in terms of RMS value of the EVM, is below -42dB for a 250Mb/s 32-PSK modulated carrier. The phase modulator, integrated in a 28nm CMOS process, consumes 31.5mW power, achieving 0.13nJ/bit energy consumption.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1141867
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