A 3.6GHz phase modulator based on a digital fractional-N PLL and a 40MHz clock can arbitrarily change the carrier phase in the ±180-degree range with 19b resolution in one clock sample. The modulation error (EVM) is below -36dB both for a 20Mb/s QPSK and a 10Mb/s GMSK modulation. The power consumption is 5mW and the core area is 0.5mm<sup>2</sup> in 65nm CMOS.

20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power

MARZIN, GIOVANNI;LEVANTINO, SALVATORE;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2012

Abstract

A 3.6GHz phase modulator based on a digital fractional-N PLL and a 40MHz clock can arbitrarily change the carrier phase in the ±180-degree range with 19b resolution in one clock sample. The modulation error (EVM) is below -36dB both for a 20Mb/s QPSK and a 10Mb/s GMSK modulation. The power consumption is 5mW and the core area is 0.5mm2 in 65nm CMOS.
Digest of Technical Papers of the 2012 IEEE International Solid-State Circuits Conference. ISSCC 2012
9781467303767
sezele; CMOS; Phase modulator; PLL; Transmitter
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/609404
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