RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

LEVANTINO, SALVATORE
 Distribuzione geografica
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Continente #
NA - Nord America 9.780
EU - Europa 3.841
AS - Asia 1.662
AF - Africa 47
SA - Sud America 40
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 7
Totale 15.385
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Nazione #
US - Stati Uniti d'America 9.639
IT - Italia 1.643
SG - Singapore 470
AT - Austria 445
VN - Vietnam 429
UA - Ucraina 279
CN - Cina 265
DE - Germania 239
IE - Irlanda 216
SE - Svezia 208
FI - Finlandia 207
GB - Regno Unito 172
CA - Canada 137
NL - Olanda 129
IN - India 114
JP - Giappone 94
JO - Giordania 81
ES - Italia 80
FR - Francia 56
KR - Corea 54
HK - Hong Kong 53
BE - Belgio 42
TW - Taiwan 34
BR - Brasile 30
GR - Grecia 21
RU - Federazione Russa 21
CH - Svizzera 20
CI - Costa d'Avorio 18
BJ - Benin 16
AL - Albania 12
ID - Indonesia 12
IR - Iran 11
MO - Macao, regione amministrativa speciale della Cina 10
TR - Turchia 8
BG - Bulgaria 7
EU - Europa 7
AZ - Azerbaigian 6
DK - Danimarca 6
EG - Egitto 6
PL - Polonia 6
EE - Estonia 5
RO - Romania 5
AR - Argentina 4
AU - Australia 4
CZ - Repubblica Ceca 4
MU - Mauritius 4
NZ - Nuova Zelanda 4
AE - Emirati Arabi Uniti 3
HU - Ungheria 3
IL - Israele 3
KG - Kirghizistan 3
KZ - Kazakistan 3
NO - Norvegia 3
HR - Croazia 2
LT - Lituania 2
PE - Perù 2
PH - Filippine 2
RS - Serbia 2
SK - Slovacchia (Repubblica Slovacca) 2
VE - Venezuela 2
AF - Afghanistan, Repubblica islamica di 1
AN - Antille olandesi 1
BD - Bangladesh 1
CL - Cile 1
CO - Colombia 1
CY - Cipro 1
GE - Georgia 1
HN - Honduras 1
JM - Giamaica 1
LA - Repubblica Popolare Democratica del Laos 1
LI - Liechtenstein 1
LK - Sri Lanka 1
MA - Marocco 1
MK - Macedonia 1
MX - Messico 1
PT - Portogallo 1
SA - Arabia Saudita 1
SC - Seychelles 1
SI - Slovenia 1
ZA - Sudafrica 1
Totale 15.385
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Città #
Fairfield 1.389
Chandler 977
Woodbridge 788
Ashburn 670
Houston 609
Wilmington 598
Santa Clara 589
Seattle 570
Milan 554
Cambridge 494
Vienna 421
Ann Arbor 384
Singapore 365
Boardman 234
Dong Ket 234
Dublin 195
Jacksonville 174
Dearborn 170
Medford 147
Lawrence 145
San Diego 99
Turin 96
Ottawa 94
Amsterdam 86
Helsinki 82
Amman 81
Beijing 79
Redwood City 68
Málaga 66
Shanghai 48
Des Moines 47
Tokyo 45
New York 38
Redmond 34
London 33
Brussels 32
Duncan 30
Columbus 28
Los Angeles 28
Legnano 27
Brescia 26
Hong Kong 25
Washington 22
Palazzolo sull'Oglio 21
Castilenti 20
Frankfurt am Main 20
Indiana 20
North York 20
Norwalk 19
Rome 19
Abidjan 18
Lappeenranta 18
Cotonou 16
Mountain View 16
Falls Church 15
Grafing 14
Verona 14
Dallas 12
Pordenone 12
Taipei 12
Auburn Hills 11
Hefei 11
Marseille 11
Naples 11
Princeton 11
Stockholm 11
Zurich 11
Chicago 10
Edinburgh 10
Groningen 10
Guangzhou 10
Jakarta 10
Kilburn 10
New Delhi 10
Pavia 10
San Francisco 10
Hanoi 9
Neubiberg 9
Pasadena 9
San Jose 9
St Louis 9
Central District 8
Chengdu 8
Madrid 8
Monza 8
Munich 8
Nanjing 8
Shenzhen 8
Toronto 8
Delhi 7
Irvine 7
Lafayette 7
São Paulo 7
Trieste 7
Atlanta 6
Baku 6
Bengaluru 6
Cortenuova 6
Fremont 6
Gurugram 6
Totale 11.554
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 216
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 173
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 171
Power-jitter trade-off analysis in digital-to-time converters 170
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 162
Bang-bang digital PLLs for wireless systems 151
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 146
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 142
Wideband chirp generation techniques in digital phase-locked loops 141
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 131
Computing low-frequency noise in charge-pump phase-locked loops 126
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops 124
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 124
Chirp Generators for Millimeter-Wave FMCW Radars 124
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 123
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 122
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 122
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing 122
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 120
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 119
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 118
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 118
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 117
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 113
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 111
Quantization effects in All-Digital Phase-Locked Loops 111
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 110
Fast-switching analog PLL with finite-impulse response 108
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 106
A multi-tank LC-oscillator 104
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation 103
Electronic device for generating a fractional frequency 103
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 102
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 102
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 102
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 101
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 101
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 101
Low Power RF Digital PLLs with Direct Carrier Modulation 101
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 101
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 100
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 99
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 99
A Glitch-Corrector Circuit for Low-Spur ADPLLs 99
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 99
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking 99
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 99
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 98
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition 98
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 98
A Circuit Technique Improving the Image Rejection of RF Front-Ends 98
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 97
A spur cancellation technique for MDLL-based frequency synthesizers 97
Analysis of power efficiency in high-performance class-B oscillators 97
A Dual-Band Frequency Synthesizer for 802.11a/b/g with Fractional-Spur Averaging Technique 96
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 96
Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops 96
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 96
A 2-GHz Low-Power Low-Noise CMOS 32/33 Prescaler 95
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 95
Integrated Frequency Synthesizers for Wireless Systems 94
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 94
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 94
A time-digital converter and an electronic system implementing the converter 93
Variation-aware Modeling of Integrated Capacitors based on Floating Random Walk Extraction 93
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 93
Noise Analysis and Minimization in Bang-Bang Digital PLLs 93
Simulating phase noise induced from cyclostationary noise sources 92
A low-phase-noise 5GHz quadrature CMOS VCO using common-mode inductive coupling 91
Impact of AAC design on phase noise performance of VCOs 90
Reducing flicker noise up-conversion in a 65nm CMOS VCO in the 1.6 to 2.6 GHz band 90
Analysis of fractional-n bang-bang digital PLLs using phase switching technique 90
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 90
AM-to-PM conversion in varactor-tuned oscillators 90
Behavioral Phase-Noise Analysis of Charge-Pump Phase-Locked Loops 88
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE 88
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 88
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 88
Phase noise and accuracy in quadrature oscillators 88
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 86
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band 86
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 86
Fast-switching analog PLL with finite-impulse response 85
An efficient method to compute phase-noise in injection-locked frequency dividers 84
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 84
Convertitore tempo-digitale e sistema elettronico impiegante il convertitore 83
Low-Power All-Analog Component Separator for an 802.11a/g LINC Transmitter 83
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 83
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) 83
Phase noise in digital frequency dividers 82
Impact of non-quasi-static effects on 1/f3 phase noise in a 1.9-to-2.6 GHz oscillator 82
Differential Tuning Oscillators with Reduced Flicker Noise Upconversion 82
Digital frequency synthesizer with robust injection locked divider 82
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing 81
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise 80
A Glitch-Corrector Circuit for Low-Spur ADPLLs 80
A low phase noise 5GHz Quadrature CMOS VCO using common mode inductive coupling 80
Background adaptive linearization of high-speed digital-to-analog converters 80
A CMOS IF sampling circuit with reduced aliasing for wireless applications 79
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling 79
Totale 10.370
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Categoria #
all - tutte 58.229
article - articoli 24.294
book - libri 330
conference - conferenze 28.457
curatela - curatele 0
other - altro 0
patent - brevetti 3.296
selected - selezionate 0
volume - volumi 1.852
Totale 116.458
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.522 0 0 0 0 0 0 371 265 342 154 291 99
2020/20212.197 197 132 212 116 159 147 112 144 140 203 113 522
2021/20221.722 74 194 152 97 132 100 97 122 135 108 265 246
2022/20232.578 234 219 92 298 299 276 38 181 438 215 201 87
2023/20241.423 88 224 105 104 156 131 116 93 26 123 49 208
2024/20251.732 60 175 211 100 803 349 34 0 0 0 0 0
Totale 15.655