RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

LEVANTINO, SALVATORE
 Distribuzione geografica
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Continente #
NA - Nord America 16.078
EU - Europa 9.371
AS - Asia 8.595
SA - Sud America 1.218
AF - Africa 386
OC - Oceania 18
Continente sconosciuto - Info sul continente non disponibili 8
Totale 35.674
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Nazione #
US - Stati Uniti d'America 15.723
RU - Federazione Russa 3.528
SG - Singapore 2.727
IT - Italia 2.314
CN - Cina 2.054
VN - Vietnam 1.090
BR - Brasile 1.024
HK - Hong Kong 616
KR - Corea 575
JP - Giappone 531
DE - Germania 475
AT - Austria 469
FR - Francia 390
NL - Olanda 329
GB - Regno Unito 328
UA - Ucraina 303
FI - Finlandia 265
IN - India 261
IE - Irlanda 243
SE - Svezia 241
CA - Canada 233
MA - Marocco 160
TW - Taiwan 156
ES - Italia 121
JO - Giordania 91
PL - Polonia 90
AR - Argentina 78
BD - Bangladesh 73
MX - Messico 70
BE - Belgio 55
ZA - Sudafrica 51
IQ - Iraq 49
TR - Turchia 47
EG - Egitto 46
ID - Indonesia 46
CI - Costa d'Avorio 36
PH - Filippine 34
PK - Pakistan 32
CH - Svizzera 31
EC - Ecuador 28
GR - Grecia 28
UZ - Uzbekistan 22
VE - Venezuela 21
AE - Emirati Arabi Uniti 20
NO - Norvegia 20
IL - Israele 19
AL - Albania 18
SA - Arabia Saudita 18
KE - Kenya 17
BJ - Benin 16
CO - Colombia 16
DK - Danimarca 15
CL - Cile 14
CZ - Repubblica Ceca 14
IR - Iran 14
TH - Thailandia 14
BG - Bulgaria 13
KZ - Kazakistan 13
AZ - Azerbaigian 12
MO - Macao, regione amministrativa speciale della Cina 12
PE - Perù 12
PT - Portogallo 12
AU - Australia 11
PY - Paraguay 11
CR - Costa Rica 10
ET - Etiopia 9
KG - Kirghizistan 9
RO - Romania 9
EE - Estonia 8
TN - Tunisia 8
BO - Bolivia 7
DZ - Algeria 7
EU - Europa 7
HU - Ungheria 7
LK - Sri Lanka 7
LT - Lituania 7
NP - Nepal 7
JM - Giamaica 6
LA - Repubblica Popolare Democratica del Laos 6
LB - Libano 6
PA - Panama 6
GE - Georgia 5
HN - Honduras 5
HR - Croazia 5
MU - Mauritius 5
NG - Nigeria 5
OM - Oman 5
RS - Serbia 5
SK - Slovacchia (Repubblica Slovacca) 5
TT - Trinidad e Tobago 5
UY - Uruguay 5
DO - Repubblica Dominicana 4
KW - Kuwait 4
NZ - Nuova Zelanda 4
PS - Palestinian Territory 4
SI - Slovenia 4
SN - Senegal 4
AO - Angola 3
BA - Bosnia-Erzegovina 3
BB - Barbados 3
Totale 35.604
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Città #
Ashburn 2.508
Singapore 1.548
Fairfield 1.389
San Jose 1.287
Chandler 978
Milan 864
Woodbridge 788
Santa Clara 628
Houston 625
Wilmington 599
Seattle 574
Hong Kong 520
Moscow 499
Cambridge 494
Seoul 482
Hefei 448
Vienna 435
Tokyo 427
Ann Arbor 384
Los Angeles 367
Beijing 340
The Dalles 320
Council Bluffs 286
Boardman 236
Dong Ket 234
Dublin 219
Ho Chi Minh City 210
Lauterbourg 189
Kent 183
Jacksonville 181
Dallas 171
Dearborn 170
Hanoi 158
North Charleston 157
Medford 147
Lawrence 145
New York 143
Amsterdam 115
Frankfurt am Main 108
Turin 103
San Diego 102
Shanghai 102
Helsinki 101
Buffalo 99
Ottawa 94
São Paulo 93
Casablanca 91
Amman 90
Taipei 90
London 76
Orem 68
Redwood City 68
Málaga 66
Kenitra 56
Las Vegas 56
Warsaw 56
Des Moines 55
Chicago 52
Munich 46
Montreal 43
Guangzhou 42
Stockholm 42
Chennai 39
Denver 38
Brussels 36
Turku 36
Abidjan 34
Brescia 34
Redmond 34
Rome 34
Da Nang 33
Mumbai 33
Sesto San Giovanni 33
Toronto 33
Columbus 32
Haiphong 31
Cairo 30
Duncan 30
Verona 29
Phoenix 28
Washington 28
Atlanta 27
Legnano 27
Rio de Janeiro 27
Salt Lake City 27
Johannesburg 25
Changsha 24
Redondo Beach 24
Belo Horizonte 23
Meguro City 23
Poplar 23
Tianjin 23
Hangzhou 21
Lappeenranta 21
Nuremberg 21
Palazzolo sull'Oglio 21
Ankara 20
Brooklyn 20
Castilenti 20
Indiana 20
Totale 22.309
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 353
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 290
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 282
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 281
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 269
Power-jitter trade-off analysis in digital-to-time converters 266
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 264
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing 263
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 257
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 256
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 254
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 250
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 243
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 238
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 237
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 235
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 234
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 230
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 227
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 226
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation 223
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 222
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 219
Chirp Generators for Millimeter-Wave FMCW Radars 218
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 217
Hybrid Resonant Switched-Capacitor Converter for 48-3.4 V Direct Conversion 216
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 214
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 212
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 207
Bang-bang digital PLLs for wireless systems 207
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 206
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 206
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops 204
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning 203
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 203
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 202
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 201
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 198
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique 197
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 197
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 197
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 197
Concurrent effect of redundancy and switching algorithms in SAR ADCs 194
A 1-A 90% Peak Efficiency 5–36-V Input Voltage Time-Based Buck Converter with Adaptive Gain Compensation and Controlled-Skip Operation 194
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 194
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 194
Fast-switching analog PLL with finite-impulse response 194
Wideband chirp generation techniques in digital phase-locked loops 194
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking 194
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 192
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 191
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition 190
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector 189
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 188
Electronic device for generating a fractional frequency 187
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 186
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 185
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 185
A multi-tank LC-oscillator 185
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 184
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 183
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 183
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 183
20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power 183
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation 182
A Low-Noise Fractional-$N$ Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC 182
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 182
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 181
A time-digital converter and an electronic system implementing the converter 181
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 180
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC 180
A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS 180
A Glitch-Corrector Circuit for Low-Spur ADPLLs 180
Noise Analysis and Minimization in Bang-Bang Digital PLLs 180
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 179
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 179
Spread-Spectrum Frequency Modulation in a DC/DC Converter With Time-Based Control 178
An efficient method to compute phase-noise in injection-locked frequency dividers 178
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE 178
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 178
A spur cancellation technique for MDLL-based frequency synthesizers 177
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 176
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters 175
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 173
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 172
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications 172
Convertitore tempo-digitale e sistema elettronico impiegante il convertitore 171
A Novel Topology of Coupled Phase-Locked Loops 170
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 169
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 169
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 169
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion 166
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 166
Calibration Techniques in Phased-Locked Loops: Theoretical basis and practical applications 165
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 165
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise 165
Low Power RF Digital PLLs with Direct Carrier Modulation 165
Computing low-frequency noise in charge-pump phase-locked loops 164
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 163
Comparing techniques for spur reduction in digital bang-bang PLLs 163
Totale 20.126
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Categoria #
all - tutte 101.025
article - articoli 42.083
book - libri 478
conference - conferenze 48.643
curatela - curatele 0
other - altro 0
patent - brevetti 6.731
selected - selezionate 0
volume - volumi 3.090
Totale 202.050
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021838 0 0 0 0 0 0 0 0 0 203 113 522
2021/20221.722 74 194 152 97 132 100 97 122 135 108 265 246
2022/20232.578 234 219 92 298 299 276 38 181 438 215 201 87
2023/20241.423 88 224 105 104 156 131 116 93 26 123 49 208
2024/20255.126 60 175 211 100 803 349 296 424 778 288 796 846
2025/202616.997 3.133 2.912 877 1.474 1.180 928 3.155 865 1.131 1.342 0 0
Totale 36.046