RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

LEVANTINO, SALVATORE
 Distribuzione geografica
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Continente #
NA - Nord America 13.323
EU - Europa 8.823
AS - Asia 5.962
SA - Sud America 1.122
AF - Africa 349
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 7
Totale 29.601
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Nazione #
US - Stati Uniti d'America 13.011
RU - Federazione Russa 3.524
SG - Singapore 2.389
IT - Italia 2.160
CN - Cina 1.675
BR - Brasile 962
VN - Vietnam 682
AT - Austria 468
DE - Germania 430
NL - Olanda 314
UA - Ucraina 296
GB - Regno Unito 291
FI - Finlandia 248
SE - Svezia 238
IE - Irlanda 237
CA - Canada 221
IN - India 213
KR - Corea 192
FR - Francia 180
JP - Giappone 159
MA - Marocco 158
ES - Italia 113
TW - Taiwan 112
HK - Hong Kong 111
JO - Giordania 88
PL - Polonia 84
AR - Argentina 70
BD - Bangladesh 54
MX - Messico 54
BE - Belgio 53
ZA - Sudafrica 47
TR - Turchia 39
EG - Egitto 38
CI - Costa d'Avorio 36
ID - Indonesia 35
IQ - Iraq 31
CH - Svizzera 29
GR - Grecia 26
NO - Norvegia 20
PK - Pakistan 20
EC - Ecuador 19
AE - Emirati Arabi Uniti 17
IL - Israele 17
UZ - Uzbekistan 17
AL - Albania 16
BJ - Benin 16
VE - Venezuela 16
DK - Danimarca 14
IR - Iran 14
CO - Colombia 13
CZ - Repubblica Ceca 13
KE - Kenya 13
KZ - Kazakistan 12
BG - Bulgaria 11
MO - Macao, regione amministrativa speciale della Cina 11
PE - Perù 11
PY - Paraguay 11
AZ - Azerbaigian 10
SA - Arabia Saudita 9
AU - Australia 8
CL - Cile 8
KG - Kirghizistan 8
RO - Romania 8
EE - Estonia 7
EU - Europa 7
CR - Costa Rica 6
ET - Etiopia 6
HU - Ungheria 6
LK - Sri Lanka 6
PT - Portogallo 6
TN - Tunisia 6
BO - Bolivia 5
GE - Georgia 5
HN - Honduras 5
LA - Repubblica Popolare Democratica del Laos 5
LT - Lituania 5
SK - Slovacchia (Repubblica Slovacca) 5
UY - Uruguay 5
JM - Giamaica 4
KW - Kuwait 4
MU - Mauritius 4
NZ - Nuova Zelanda 4
PA - Panama 4
PS - Palestinian Territory 4
RS - Serbia 4
TT - Trinidad e Tobago 4
BB - Barbados 3
DZ - Algeria 3
LU - Lussemburgo 3
LV - Lettonia 3
NG - Nigeria 3
PH - Filippine 3
SN - Senegal 3
AM - Armenia 2
BF - Burkina Faso 2
BH - Bahrain 2
BY - Bielorussia 2
CY - Cipro 2
DM - Dominica 2
DO - Repubblica Dominicana 2
Totale 29.552
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Città #
Ashburn 1.926
Fairfield 1.389
Singapore 1.328
Chandler 977
Milan 793
Woodbridge 788
Houston 623
Santa Clara 610
Wilmington 599
Seattle 572
Moscow 498
Cambridge 494
Hefei 448
Vienna 434
Ann Arbor 384
Beijing 320
Boardman 234
Dong Ket 234
Los Angeles 233
San Jose 232
Dublin 213
Council Bluffs 199
Kent 183
Jacksonville 179
Dearborn 170
Medford 147
Lawrence 145
New York 128
Seoul 110
Dallas 108
Amsterdam 104
San Diego 102
Ho Chi Minh City 101
Turin 101
Buffalo 95
Ottawa 94
Casablanca 91
Amman 88
Helsinki 85
São Paulo 85
Shanghai 83
Tokyo 83
Hong Kong 79
Frankfurt am Main 77
Redwood City 68
London 66
Málaga 66
Hanoi 65
Kenitra 56
Taipei 55
Des Moines 54
Warsaw 52
Chicago 46
Munich 46
Orem 44
Stockholm 41
Montreal 38
Brussels 36
Denver 36
Turku 36
Abidjan 34
Redmond 34
Sesto San Giovanni 33
Brescia 32
Columbus 30
Duncan 30
Toronto 30
Verona 29
Guangzhou 28
Legnano 27
Rome 27
Atlanta 26
Cairo 26
Chennai 26
Mumbai 26
Johannesburg 25
Washington 25
Phoenix 24
Redondo Beach 24
Rio de Janeiro 24
Meguro City 23
The Dalles 23
Belo Horizonte 22
Palazzolo sull'Oglio 21
Poplar 21
Castilenti 20
Indiana 20
Lappeenranta 20
North York 20
Oslo 20
Brooklyn 19
Norwalk 19
Ankara 18
New Delhi 18
Roubaix 18
Changsha 17
Hangzhou 17
Mexico City 17
Nanjing 17
Nuremberg 17
Totale 17.718
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 305
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 257
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 246
Power-jitter trade-off analysis in digital-to-time converters 245
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 238
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 237
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 232
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 230
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing 223
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 216
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 214
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 211
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 205
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 203
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 201
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation 199
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 195
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 191
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 190
Bang-bang digital PLLs for wireless systems 190
Chirp Generators for Millimeter-Wave FMCW Radars 189
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 189
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 187
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops 186
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 183
Wideband chirp generation techniques in digital phase-locked loops 178
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 177
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 176
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 176
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 176
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 175
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 174
Hybrid Resonant Switched-Capacitor Converter for 48-3.4 V Direct Conversion 172
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 171
Fast-switching analog PLL with finite-impulse response 167
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 166
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 166
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 166
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 165
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 164
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition 164
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 163
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 162
A 1-A 90% Peak Efficiency 5–36-V Input Voltage Time-Based Buck Converter with Adaptive Gain Compensation and Controlled-Skip Operation 161
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 160
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 160
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 159
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking 159
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 158
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 157
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 156
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 156
Electronic device for generating a fractional frequency 156
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 156
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 155
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 155
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 154
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 153
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 153
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation 152
Computing low-frequency noise in charge-pump phase-locked loops 152
Noise Analysis and Minimization in Bang-Bang Digital PLLs 152
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 150
A time-digital converter and an electronic system implementing the converter 150
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 150
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 150
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 150
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 149
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 149
A Glitch-Corrector Circuit for Low-Spur ADPLLs 149
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 149
Spread-Spectrum Frequency Modulation in a DC/DC Converter With Time-Based Control 148
A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS 148
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters 148
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 148
A spur cancellation technique for MDLL-based frequency synthesizers 148
20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power 148
A multi-tank LC-oscillator 148
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications 146
Low Power RF Digital PLLs with Direct Carrier Modulation 145
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique 144
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 144
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 144
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 143
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 143
Quantization effects in All-Digital Phase-Locked Loops 143
Calibration Techniques in Phased-Locked Loops: Theoretical basis and practical applications 142
Analysis of power efficiency in high-performance class-B oscillators 142
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC 141
Simulating phase noise induced from cyclostationary noise sources 141
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE 141
Concurrent effect of redundancy and switching algorithms in SAR ADCs 140
Integrated Frequency Synthesizers for Wireless Systems 140
An efficient method to compute phase-noise in injection-locked frequency dividers 139
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 138
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 138
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 138
Comparing techniques for spur reduction in digital bang-bang PLLs 138
Phase noise and accuracy in quadrature oscillators 137
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band 136
Totale 16.869
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Categoria #
all - tutte 91.558
article - articoli 38.077
book - libri 447
conference - conferenze 44.256
curatela - curatele 0
other - altro 0
patent - brevetti 5.981
selected - selezionate 0
volume - volumi 2.797
Totale 183.116
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.234 0 0 0 0 0 0 112 144 140 203 113 522
2021/20221.722 74 194 152 97 132 100 97 122 135 108 265 246
2022/20232.578 234 219 92 298 299 276 38 181 438 215 201 87
2023/20241.423 88 224 105 104 156 131 116 93 26 123 49 208
2024/20255.126 60 175 211 100 803 349 296 424 778 288 796 846
2025/202610.915 3.133 2.912 877 1.474 1.180 928 411 0 0 0 0 0
Totale 29.964