RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

LEVANTINO, SALVATORE
 Distribuzione geografica
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Continente #
NA - Nord America 8.870
EU - Europa 3.435
AS - Asia 1.061
AF - Africa 29
SA - Sud America 17
Continente sconosciuto - Info sul continente non disponibili 7
OC - Oceania 7
Totale 13.426
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Nazione #
US - Stati Uniti d'America 8.745
IT - Italia 1.458
AT - Austria 431
VN - Vietnam 429
UA - Ucraina 261
DE - Germania 216
SE - Svezia 207
CN - Cina 206
FI - Finlandia 194
IE - Irlanda 190
GB - Regno Unito 159
CA - Canada 123
IN - India 91
JP - Giappone 84
JO - Giordania 81
ES - Italia 77
NL - Olanda 64
HK - Hong Kong 51
FR - Francia 45
BE - Belgio 41
KR - Corea 39
TW - Taiwan 31
GR - Grecia 20
CI - Costa d'Avorio 18
CH - Svizzera 14
BR - Brasile 13
SG - Singapore 13
AL - Albania 12
IR - Iran 10
MO - Macao, regione amministrativa speciale della Cina 9
EU - Europa 7
DK - Danimarca 6
PL - Polonia 6
BG - Bulgaria 5
RO - Romania 5
RU - Federazione Russa 5
TR - Turchia 5
EG - Egitto 4
MU - Mauritius 4
NZ - Nuova Zelanda 4
AU - Australia 3
EE - Estonia 3
HU - Ungheria 3
AR - Argentina 2
AZ - Azerbaigian 2
HR - Croazia 2
ID - Indonesia 2
IL - Israele 2
RS - Serbia 2
SK - Slovacchia (Repubblica Slovacca) 2
AE - Emirati Arabi Uniti 1
AF - Afghanistan, Repubblica islamica di 1
AN - Antille olandesi 1
CO - Colombia 1
CY - Cipro 1
CZ - Repubblica Ceca 1
GE - Georgia 1
HN - Honduras 1
KZ - Kazakistan 1
LI - Liechtenstein 1
LK - Sri Lanka 1
LT - Lituania 1
MA - Marocco 1
MK - Macedonia 1
NO - Norvegia 1
PE - Perù 1
PT - Portogallo 1
SC - Seychelles 1
SI - Slovenia 1
ZA - Sudafrica 1
Totale 13.426
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Città #
Fairfield 1.389
Chandler 977
Woodbridge 788
Ashburn 664
Houston 609
Wilmington 598
Seattle 570
Cambridge 494
Milan 491
Vienna 411
Ann Arbor 384
Dong Ket 234
Jacksonville 174
Dearborn 170
Dublin 170
Medford 147
Lawrence 145
San Diego 99
Turin 95
Ottawa 88
Amman 81
Helsinki 79
Beijing 71
Redwood City 68
Málaga 66
Des Moines 47
Shanghai 37
Tokyo 37
Redmond 34
Brussels 31
Duncan 30
Columbus 28
New York 28
Amsterdam 27
Legnano 27
London 26
Boardman 24
Hong Kong 24
Washington 21
Brescia 20
Indiana 20
Los Angeles 20
North York 20
Norwalk 19
Abidjan 18
Rome 18
Mountain View 16
Falls Church 15
Grafing 14
Dallas 12
Pordenone 12
Auburn Hills 11
Hefei 11
Marseille 11
Princeton 11
Chicago 10
Edinburgh 10
Groningen 10
Kilburn 10
San Francisco 10
Stockholm 10
Taipei 10
Hanoi 9
Neubiberg 9
Pasadena 9
San Jose 9
St Louis 9
Central District 8
Frankfurt am Main 8
Guangzhou 8
Lappeenranta 8
New Delhi 8
Zurich 8
Irvine 7
Lafayette 7
Nanjing 7
Naples 7
Pavia 7
São Paulo 7
Verona 7
Bengaluru 6
Cortenuova 6
Fremont 6
Lodi 6
Madrid 6
Miami 6
Saronno 6
Shenzhen 6
Taiyuan 6
Trieste 6
Americana 5
Bergamo 5
Cork 5
Delft 5
Fara Gera D'adda 5
Genoa 5
Goodyear 5
Hounslow 5
Hsinchu 5
Jinan 5
Totale 10.053
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 206
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 167
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 154
Power-jitter trade-off analysis in digital-to-time converters 153
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 153
Bang-bang digital PLLs for wireless systems 142
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 135
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 131
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 121
Computing low-frequency noise in charge-pump phase-locked loops 120
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO 114
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 114
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 114
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops 113
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 112
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 112
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 112
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs 111
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 111
Efficient Calculation of the Impulse Sensitivity Function in Oscillators 109
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs 108
Quantization effects in All-Digital Phase-Locked Loops 107
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing 106
Chirp Generators for Millimeter-Wave FMCW Radars 103
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 102
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 102
Fast-switching analog PLL with finite-impulse response 101
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 100
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter 97
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 97
A multi-tank LC-oscillator 97
Low Power RF Digital PLLs with Direct Carrier Modulation 96
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 95
Electronic device for generating a fractional frequency 95
Wideband chirp generation techniques in digital phase-locked loops 94
A wideband voltage-biased LC oscillator with reduced flicker noise up-conversion 93
Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops 93
A Circuit Technique Improving the Image Rejection of RF Front-Ends 93
Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators 92
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 92
Analysis of power efficiency in high-performance class-B oscillators 92
A Dual-Band Frequency Synthesizer for 802.11a/b/g with Fractional-Spur Averaging Technique 91
A spur cancellation technique for MDLL-based frequency synthesizers 91
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 91
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 91
A 2-GHz Low-Power Low-Noise CMOS 32/33 Prescaler 90
Integrated Frequency Synthesizers for Wireless Systems 89
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 89
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 89
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking 89
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 89
Variation-aware Modeling of Integrated Capacitors based on Floating Random Walk Extraction 89
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 89
A Glitch-Corrector Circuit for Low-Spur ADPLLs 88
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 88
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 88
A low-phase-noise 5GHz quadrature CMOS VCO using common-mode inductive coupling 87
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition 87
AM-to-PM conversion in varactor-tuned oscillators 87
A simulation technique to compute phase noise induced from cyclostationary noise sources in RF oscillators 86
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 86
Impact of AAC design on phase noise performance of VCOs 85
A time-digital converter and an electronic system implementing the converter 85
Simulating phase noise induced from cyclostationary noise sources 85
Analysis of fractional-n bang-bang digital PLLs using phase switching technique 85
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 85
Time-to-digital converter with 3-ps resolution and digital linearization algorithm 84
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 84
Reducing flicker noise up-conversion in a 65nm CMOS VCO in the 1.6 to 2.6 GHz band 84
Noise Analysis and Minimization in Bang-Bang Digital PLLs 84
Fast-switching analog PLL with finite-impulse response 83
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE 81
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation 80
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band 80
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic 80
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 80
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 79
An efficient method to compute phase-noise in injection-locked frequency dividers 78
Impact of non-quasi-static effects on 1/f3 phase noise in a 1.9-to-2.6 GHz oscillator 78
Low-Power All-Analog Component Separator for an 802.11a/g LINC Transmitter 78
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 78
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling 77
Differential Tuning Oscillators with Reduced Flicker Noise Upconversion 77
A CMOS IF sampling circuit with reduced aliasing for wireless applications 76
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band 76
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing 76
Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL 76
Behavioral Phase-Noise Analysis of Charge-Pump Phase-Locked Loops 76
Phase noise and accuracy in quadrature oscillators 76
Phase noise in digital frequency dividers 75
Convertitore tempo-digitale e sistema elettronico impiegante il convertitore 75
A low phase noise 5GHz Quadrature CMOS VCO using common mode inductive coupling 75
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) 75
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 75
A fully-integrated low-power low-noise 2.6-GHz bipolar VCO for wireless applications 75
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 75
Digital frequency synthesizer with robust injection locked divider 74
Background adaptive linearization of high-speed digital-to-analog converters 74
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise 73
A Glitch-Corrector Circuit for Low-Spur ADPLLs 72
Totale 9.497
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Categoria #
all - tutte 43.298
article - articoli 18.104
book - libri 281
conference - conferenze 21.335
curatela - curatele 0
other - altro 0
patent - brevetti 2.155
selected - selezionate 0
volume - volumi 1.423
Totale 86.596
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019884 0 0 0 0 0 0 0 0 0 0 459 425
2019/20203.003 212 149 80 246 396 398 371 265 342 154 291 99
2020/20212.197 197 132 212 116 159 147 112 144 140 203 113 522
2021/20221.722 74 194 152 97 132 100 97 122 135 108 265 246
2022/20232.578 234 219 92 298 299 276 38 181 438 215 201 87
2023/20241.169 88 224 105 104 156 131 116 93 26 123 3 0
Totale 13.669