LEVANTINO, SALVATORE
 Distribuzione geografica
Continente #
EU - Europa 1.699
AS - Asia 1.459
NA - Nord America 1.388
AF - Africa 70
SA - Sud America 28
OC - Oceania 21
Continente sconosciuto - Info sul continente non disponibili 8
Totale 4.673
Nazione #
US - Stati Uniti d'America 1.307
IT - Italia 821
TW - Taiwan 308
CN - Cina 262
JP - Giappone 201
IN - India 168
KR - Corea 158
DE - Germania 139
FR - Francia 108
NL - Olanda 105
HK - Hong Kong 81
IE - Irlanda 73
CA - Canada 69
VN - Vietnam 64
GB - Regno Unito 58
AT - Austria 51
CH - Svizzera 44
IR - Iran 44
RU - Federazione Russa 44
SE - Svezia 41
EG - Egitto 38
SG - Singapore 36
CZ - Repubblica Ceca 35
MO - Macao, regione amministrativa speciale della Cina 35
BE - Belgio 32
IL - Israele 32
GR - Grecia 24
AU - Australia 21
ES - Italia 20
PL - Polonia 18
RO - Romania 15
TR - Turchia 15
FI - Finlandia 14
UA - Ucraina 13
ID - Indonesia 12
PT - Portogallo 12
ZA - Sudafrica 12
AR - Argentina 11
MY - Malesia 10
NO - Norvegia 9
LY - Libia 8
IQ - Iraq 7
MX - Messico 7
SA - Arabia Saudita 7
AE - Emirati Arabi Uniti 6
BR - Brasile 6
DK - Danimarca 6
BG - Bulgaria 5
A2 - ???statistics.table.value.countryCode.A2??? 4
EU - Europa 4
LT - Lituania 4
LU - Lussemburgo 4
PE - Perù 4
PH - Filippine 4
DZ - Algeria 3
NP - Nepal 3
RS - Serbia 3
BO - Bolivia 2
BZ - Belize 2
CO - Colombia 2
EC - Ecuador 2
ET - Etiopia 2
TH - Thailandia 2
TN - Tunisia 2
AN - Antille olandesi 1
BW - Botswana 1
CM - Camerun 1
CR - Costa Rica 1
CY - Cipro 1
GE - Georgia 1
JM - Giamaica 1
KE - Kenya 1
LK - Sri Lanka 1
LV - Lettonia 1
NG - Nigeria 1
PK - Pakistan 1
RW - Ruanda 1
VE - Venezuela 1
Totale 4.673
Città #
Milan 268
Taipei 146
Shanghai 83
Houston 80
Ann Arbor 66
Tokyo 63
Ashburn 61
Fairfield 59
San Jose 50
Dublin 40
Duncan 40
Seattle 40
Bengaluru 36
Dong Ket 34
Hsinchu 32
Los Angeles 32
Central 31
Zurich 30
Atlanta 28
Seoul 28
Cambridge 27
Boardman 25
Cairo 24
Santa Cruz 24
Santa Clara 23
Woodbridge 23
Amsterdam 22
Chicago 22
Buffalo 21
Dún Laoghaire 21
Hyderabad 21
Redmond 21
Singapore 21
Beijing 19
Irvine 18
San Diego 18
Turin 18
San Francisco 17
Nanjing 16
Shenzhen 16
Wilmington 16
New Taipei 15
Daan 14
Milpitas 14
Rome 14
Stockholm 14
Vienna 14
Gwanak-gu 13
Guangzhou 12
Hangzhou 12
Hanoi 12
Macao 12
New York 12
San Clemente 12
Taichung 12
Vancouver 12
Jakarta 11
Melbourne 11
Yokohama 11
Chengdu 10
Codroipo 10
Delft 10
Frankfurt am Main 10
Mumbai 10
Ottawa 10
Paris 10
Pavia 10
Saronno 10
Toronto 10
Cascais 9
Council Bluffs 9
Kanata 9
Legnano 9
Leuven 9
Mar del Plata 9
Moscow 9
Sunnyvale 9
Buk-gu 8
Central District 8
Dallas 8
Eindhoven 8
Guiyang 8
Gurgaon 8
Helsinki 8
Lecco 8
Madrid 8
Phoenix 8
Tel Aviv 8
Zhubei 8
Berlin 7
Carlisle 7
Jaipur 7
Leawood 7
Taoyuan District 7
Villach 7
Boston 6
Bucharest 6
Chiyoda-ku 6
Cologne 6
Columbus 6
Totale 2.247
Nome #
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops, file e0c31c0d-94de-4599-e053-1705fe0aef77 1.475
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation, file e0c31c0c-4b31-4599-e053-1705fe0aef77 869
Phase Noise of Pulse Injection-Locked Oscillators, file e0c31c0d-dfb9-4599-e053-1705fe0aef77 519
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs, file e0c31c0d-4524-4599-e053-1705fe0aef77 426
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop, file e0c31c0e-47f7-4599-e053-1705fe0aef77 398
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing, file e0c31c10-5332-4599-e053-1705fe0aef77 234
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking, file e0c31c0c-9156-4599-e053-1705fe0aef77 195
A Digital PLL with Multi-tap LMS-based Bandwidth Control, file e0c31c12-dd1b-4599-e053-1705fe0aef77 156
Chirp Generators for Millimeter-Wave FMCW Radars, file e0c31c0e-a286-4599-e053-1705fe0aef77 155
Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing, file e0c31c11-5700-4599-e053-1705fe0aef77 44
Digital frequency synthesizer with robust injection locked divider, file e0c31c0c-7644-4599-e053-1705fe0aef77 17
Digital frequency synthesizer with robust injection locked divider, file e0c31c0c-7645-4599-e053-1705fe0aef77 15
Digital frequency synthesizer with robust injection locked divider, file e0c31c10-f774-4599-e053-1705fe0aef77 8
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping, file e0c31c11-bdec-4599-e053-1705fe0aef77 8
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops, file e0c31c0b-a254-4599-e053-1705fe0aef77 7
Jitter Minimization in Digital PLLs with Mid-Rise TDCs, file e0c31c0f-c8a4-4599-e053-1705fe0aef77 7
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL, file e0c31c0f-c8a5-4599-e053-1705fe0aef77 7
A Background Calibration Technique to Control the Bandwidth of Digital PLLs, file e0c31c0c-6b87-4599-e053-1705fe0aef77 6
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop, file e0c31c08-feeb-4599-e053-1705fe0aef77 5
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique, file e0c31c0b-451d-4599-e053-1705fe0aef77 5
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique, file e0c31c0c-2ee5-4599-e053-1705fe0aef77 5
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter, file e0c31c0f-e17e-4599-e053-1705fe0aef77 5
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter, file e0c31c11-f3b5-4599-e053-1705fe0aef77 5
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time, file db11cd2e-cd55-4290-9394-880935980067 4
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops, file e0c31c08-0cef-4599-e053-1705fe0aef77 4
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs, file e0c31c08-2f1c-4599-e053-1705fe0aef77 4
A Background Calibration Technique to Control the Bandwidth of Digital PLLs, file e0c31c0c-9543-4599-e053-1705fe0aef77 4
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power, file e0c31c0e-8012-4599-e053-1705fe0aef77 4
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays, file e0c31c10-a067-4599-e053-1705fe0aef77 4
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS, file e0c31c11-979a-4599-e053-1705fe0aef77 4
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology, file e0c31c11-fda6-4599-e053-1705fe0aef77 4
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter, file e0c31c12-7d9f-4599-e053-1705fe0aef77 4
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise, file e0c31c12-991b-4599-e053-1705fe0aef77 4
Hybrid Resonant Switched-Capacitor Converter for 48 V to 3.4 V Direct Conversion, file 4c7dcda5-9675-4026-b62c-79361c97e6c2 3
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters, file 9f5eaa99-a48e-4293-97f0-0d9351fea4e3 3
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion, file e0c31c08-2db5-4599-e053-1705fe0aef77 3
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic, file e0c31c08-3ec8-4599-e053-1705fe0aef77 3
Bang-Bang Digital PLLs, file e0c31c09-cf7c-4599-e053-1705fe0aef77 3
Variation-aware Modeling of Integrated Capacitors based on Floating Random Walk Extraction, file e0c31c0b-df38-4599-e053-1705fe0aef77 3
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking, file e0c31c0f-24eb-4599-e053-1705fe0aef77 3
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking, file e0c31c0f-e180-4599-e053-1705fe0aef77 3
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking, file e0c31c10-007c-4599-e053-1705fe0aef77 3
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking, file e0c31c10-bae6-4599-e053-1705fe0aef77 3
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters, file 00c77365-1dcb-4f0d-a732-886efb41bd7e 2
Concurrent effect of redundancy and switching algorithms in SAR ADCs, file 1089a64e-001b-40d2-8394-318f0dcf4977 2
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology, file 4523210a-27a0-421c-af9b-f29342b35708 2
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering, file 45fbfbe8-b126-4d65-8a02-d11dbd80de63 2
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control, file 5de6ce3b-30df-4a92-a637-16ba8e557544 2
Frequency Synthesizers for 5G Applications, file 6a958f3e-85ca-49ed-a51f-1332890ed26b 2
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, file dc36e857-1ff2-4898-8361-0b0ee66b3f1f 2
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion, file e0c31c07-ce7a-4599-e053-1705fe0aef77 2
A Wideband 3.6 GHz Digital Delta-Sigma Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation, file e0c31c07-e282-4599-e053-1705fe0aef77 2
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration, file e0c31c07-f357-4599-e053-1705fe0aef77 2
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power, file e0c31c08-072d-4599-e053-1705fe0aef77 2
A Background calibration technique to control bandwidth in digital PLLs, file e0c31c08-19fa-4599-e053-1705fe0aef77 2
Phase Noise of Pulse Injection-Locked Oscillators, file e0c31c08-1e0c-4599-e053-1705fe0aef77 2
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs, file e0c31c08-1f3d-4599-e053-1705fe0aef77 2
General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL, file e0c31c08-29f9-4599-e053-1705fe0aef77 2
Automatic Amplitude Control Loop for a 2-V, 2.5-GHz LC-tank VCO, file e0c31c08-2ea7-4599-e053-1705fe0aef77 2
A 2-GHz Low-Power Low-Noise CMOS 32/33 Prescaler, file e0c31c08-2fc3-4599-e053-1705fe0aef77 2
Power-jitter trade-off analysis in digital-to-time converters, file e0c31c0a-5693-4599-e053-1705fe0aef77 2
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL, file e0c31c0b-3c65-4599-e053-1705fe0aef77 2
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops, file e0c31c0b-c4e7-4599-e053-1705fe0aef77 2
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique, file e0c31c0b-eb91-4599-e053-1705fe0aef77 2
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops, file e0c31c0d-7968-4599-e053-1705fe0aef77 2
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs, file e0c31c10-f770-4599-e053-1705fe0aef77 2
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability, file e0c31c11-6394-4599-e053-1705fe0aef77 2
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs, file e0c31c11-7592-4599-e053-1705fe0aef77 2
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, file e0c31c12-dd20-4599-e053-1705fe0aef77 2
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations, file 0e47c3ec-5efd-49ea-ae15-6591f23d752b 1
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology, file 3b849264-853c-4047-a1d1-10ec7412ce85 1
A Compact High-Efficiency Boost Converter With Time-Based Control, RHP Zero-Elimination, and Tracking Error Compensation, file 3be8ffe8-4a1e-4fbe-a06b-a26e08f3c870 1
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise, file 4b178ef4-db41-4f6d-970d-d982e17d0fd8 1
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC), file 69536edd-1d24-40d4-b563-6e94f62b3832 1
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation, file 852a99af-f812-45c4-9507-d7aaae14891a 1
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping, file 93c4ea14-083d-4128-900f-e6ddf7934922 1
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation, file a12bb658-1f2b-457e-807e-0c3f49f61ad2 1
Quantization effects in All-Digital Phase-Locked Loops, file e0c31c07-bf9b-4599-e053-1705fe0aef77 1
A Circuit Technique Improving the Image Rejection of RF Front-Ends, file e0c31c07-c04b-4599-e053-1705fe0aef77 1
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter, file e0c31c07-c163-4599-e053-1705fe0aef77 1
Impact of AAC design on phase noise performance of VCOs, file e0c31c07-c2bd-4599-e053-1705fe0aef77 1
AM-to-PM conversion in varactor-tuned oscillators, file e0c31c07-c2f0-4599-e053-1705fe0aef77 1
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs, file e0c31c07-cc4f-4599-e053-1705fe0aef77 1
Integrated LC oscillators for frequency synthesis in wireless applications, file e0c31c07-cefb-4599-e053-1705fe0aef77 1
A fully-integrated low-power low-noise 2.6-GHz bipolar VCO for wireless applications, file e0c31c07-cf8d-4599-e053-1705fe0aef77 1
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop, file e0c31c07-d011-4599-e053-1705fe0aef77 1
Multiphase LC Oscillators, file e0c31c07-d3ba-4599-e053-1705fe0aef77 1
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS, file e0c31c07-d657-4599-e053-1705fe0aef77 1
Phase noise in digital frequency dividers, file e0c31c07-d9fd-4599-e053-1705fe0aef77 1
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider, file e0c31c07-daf9-4599-e053-1705fe0aef77 1
Differentially-Tuned VCO with Reduced Tuning Sensitivity and Flicker Noise Up-Conversion, file e0c31c07-db64-4599-e053-1705fe0aef77 1
Fast-switching analog PLL with finite-impulse response, file e0c31c07-db79-4599-e053-1705fe0aef77 1
Behavioral Phase-Noise Analysis of Charge-Pump Phase-Locked Loops, file e0c31c07-dcd4-4599-e053-1705fe0aef77 1
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division, file e0c31c07-de91-4599-e053-1705fe0aef77 1
Electronic device for generating a fractional frequency, file e0c31c07-dfc2-4599-e053-1705fe0aef77 1
Electronic device for generating a fractional frequency, file e0c31c07-dfc3-4599-e053-1705fe0aef77 1
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power, file e0c31c07-e2b0-4599-e053-1705fe0aef77 1
Low-Power Divider Retiming in a 3-4GHz Fractional-N PLL, file e0c31c07-e2e2-4599-e053-1705fe0aef77 1
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power, file e0c31c07-e2e3-4599-e053-1705fe0aef77 1
Multipath Adaptive Cancellation of Divider Non-Linearity in Fractional-N PLLs, file e0c31c07-e2e4-4599-e053-1705fe0aef77 1
Totale 4.724
Categoria #
all - tutte 8.016
article - articoli 7.408
book - libri 0
conference - conferenze 103
curatela - curatele 0
other - altro 0
patent - brevetti 207
selected - selezionate 0
volume - volumi 298
Totale 16.032


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201916 0 0 0 0 0 0 0 0 0 0 11 5
2019/2020178 4 5 0 5 14 16 21 18 32 15 32 16
2020/2021860 59 67 30 35 53 93 62 80 87 95 77 122
2021/20221.255 92 122 82 170 126 74 122 90 138 62 125 52
2022/20231.057 52 94 76 86 87 77 89 108 113 92 86 97
2023/20241.289 89 99 102 105 123 121 121 170 150 123 86 0
Totale 4.770