A 2-GHz Low-Power Low-Noise CMOS 32/33 Prescaler

This paper presents a dual-phase 32/33 dual-modulus prescaler integrated in 0.35-mm CMOS technology. The design is specifically oriented to minimize the power dissipation, while maintaining the required speed. The first stage employs a dynamic pseudo-nMOS logic with reduced complexity, while the four subsequent ¸2- dividers are implemented in true-single-phase-clock logic. The power dissipation results as low as 3.6 mW at 2 GHz and it is about 5 times lower than a sourcecoupled- logic implementation. This result is obtained with no penalty on phase noise, which measures –169 dBc/Hz at 60-MHz output.