A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-μm CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing
LEVANTINO, SALVATORE;SAMORI, CARLO;
2003-01-01
Abstract
A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-μm CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.File in questo prodotto:
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2003_JSSC_10.1109JSSC.2003.811871.pdf
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