The paper presents a comprehensive analysis of signal intermixing taking place across the injectors of frequency-divide-by-three circuits with divide-by-two secondary locking. The analytical results confirmed by circuit simulations provide an insightful understanding of the circuit operation, and inspire the design of a novel single-inductor injection-locked frequency divider (ILFD) by three, where injection is reinforced by a dual-injection scheme with no penalty in power dissipation. The novel circuit, when benchmarked against existing ILFD topologies, optimized in a 65-nm LP CMOS process, shows about a three-time larger locking range with respect to the single-inductor divider by three with a floating-source injector, and about a 40% improvement with respect to the single-inductor divider by three with divide-by-two locking, for the same power dissipation. The novel topology has been adopted in a 15-GHz divider by three for a 5G radio-frequency synthesizer, reaching a 23.6% locking range at 1.56-mW dc power, featuring one of the best performances among divide-by-three ILFDs and a compact size of only 0.09 mm².

A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking

GARGHETTI, ALESSANDRO;Andrea L. Lacaita;Salvatore Levantino
2018-01-01

Abstract

The paper presents a comprehensive analysis of signal intermixing taking place across the injectors of frequency-divide-by-three circuits with divide-by-two secondary locking. The analytical results confirmed by circuit simulations provide an insightful understanding of the circuit operation, and inspire the design of a novel single-inductor injection-locked frequency divider (ILFD) by three, where injection is reinforced by a dual-injection scheme with no penalty in power dissipation. The novel circuit, when benchmarked against existing ILFD topologies, optimized in a 65-nm LP CMOS process, shows about a three-time larger locking range with respect to the single-inductor divider by three with a floating-source injector, and about a 40% improvement with respect to the single-inductor divider by three with divide-by-two locking, for the same power dissipation. The novel topology has been adopted in a 15-GHz divider by three for a 5G radio-frequency synthesizer, reaching a 23.6% locking range at 1.56-mW dc power, featuring one of the best performances among divide-by-three ILFDs and a compact size of only 0.09 mm².
2018
CMOS, RF, frequency divider, injection locking, communications, mm-wave
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1066456
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