This paper describes a method for speeding up the linear settling response of integer-N phase-locked loops. Extending the discrete-time model of the PLL first proposed by Gardner, simple design rules are derived which guarantee accurate frequency settling in few reference cycles. Simulations show that the proposed design technique improves up to six times the settling time of a conventional design. The stability margins and the noise behavior of the proposed system are analyzed.

Fast-switching analog PLL with finite-impulse response

LEVANTINO, SALVATORE;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2004-01-01

Abstract

This paper describes a method for speeding up the linear settling response of integer-N phase-locked loops. Extending the discrete-time model of the PLL first proposed by Gardner, simple design rules are derived which guarantee accurate frequency settling in few reference cycles. Simulations show that the proposed design technique improves up to six times the settling time of a conventional design. The stability margins and the noise behavior of the proposed system are analyzed.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/555507
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