A 0.25 μm BiCMOS spur-compensated fractional-N PLL is implemented in an IEEE 802.11a/b/g zero-IF transceiver. The synthesizer covers the 2.4 to 2.5GHz and the 5.1 to 5.9GHz bands with 0.5MHz and 5MHz resolution, respectively. The phase noise integrated from 10kHz to 10MHz is lower than 1.25° rms for any synthesized carrier. The power consumption is 39/59mW mode from 2.5V supply.
A Dual-Band Frequency Synthesizer for 802.11a/b/g with Fractional-Spur Averaging Technique
LEVANTINO, SALVATORE;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2005-01-01
Abstract
A 0.25 μm BiCMOS spur-compensated fractional-N PLL is implemented in an IEEE 802.11a/b/g zero-IF transceiver. The synthesizer covers the 2.4 to 2.5GHz and the 5.1 to 5.9GHz bands with 0.5MHz and 5MHz resolution, respectively. The phase noise integrated from 10kHz to 10MHz is lower than 1.25° rms for any synthesized carrier. The power consumption is 39/59mW mode from 2.5V supply.File in questo prodotto:
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