LACAITA, ANDREA LEONARDO
 Distribuzione geografica
Continente #
NA - Nord America 38.999
EU - Europa 20.556
AS - Asia 13.941
SA - Sud America 2.590
AF - Africa 595
OC - Oceania 39
Continente sconosciuto - Info sul continente non disponibili 18
Totale 76.738
Nazione #
US - Stati Uniti d'America 38.176
RU - Federazione Russa 6.839
IT - Italia 5.084
SG - Singapore 4.483
CN - Cina 3.547
BR - Brasile 2.193
VN - Vietnam 2.187
UA - Ucraina 1.426
DE - Germania 1.254
AT - Austria 1.036
SE - Svezia 891
FR - Francia 791
HK - Hong Kong 785
KR - Corea 776
FI - Finlandia 738
GB - Regno Unito 736
CA - Canada 603
JP - Giappone 571
NL - Olanda 452
IE - Irlanda 447
IN - India 346
MA - Marocco 291
ES - Italia 228
TW - Taiwan 204
BD - Bangladesh 180
BE - Belgio 149
AR - Argentina 135
PL - Polonia 133
JO - Giordania 128
MX - Messico 110
TR - Turchia 108
ZA - Sudafrica 91
IQ - Iraq 89
ID - Indonesia 76
EC - Ecuador 62
PK - Pakistan 60
CH - Svizzera 51
PH - Filippine 49
CI - Costa d'Avorio 46
EG - Egitto 45
CO - Colombia 44
UZ - Uzbekistan 43
VE - Venezuela 41
SA - Arabia Saudita 38
IL - Israele 33
CL - Cile 30
AU - Australia 29
PY - Paraguay 29
AZ - Azerbaigian 28
CZ - Repubblica Ceca 28
RO - Romania 28
PT - Portogallo 25
TH - Thailandia 25
BG - Bulgaria 24
CR - Costa Rica 24
LT - Lituania 24
GR - Grecia 22
PE - Perù 21
AE - Emirati Arabi Uniti 20
HU - Ungheria 20
KE - Kenya 20
KZ - Kazakistan 20
TN - Tunisia 20
AL - Albania 19
JM - Giamaica 19
IR - Iran 18
KG - Kirghizistan 17
DZ - Algeria 16
UY - Uruguay 16
BO - Bolivia 15
EU - Europa 15
DK - Danimarca 13
EE - Estonia 13
LV - Lettonia 13
NP - Nepal 13
LB - Libano 12
PA - Panama 12
ET - Etiopia 11
SI - Slovenia 11
LA - Repubblica Popolare Democratica del Laos 10
HR - Croazia 9
MD - Moldavia 9
MO - Macao, regione amministrativa speciale della Cina 9
TT - Trinidad e Tobago 9
DO - Repubblica Dominicana 8
NI - Nicaragua 8
OM - Oman 8
SN - Senegal 8
GE - Georgia 7
HN - Honduras 7
MK - Macedonia 7
MU - Mauritius 7
MY - Malesia 7
NO - Norvegia 7
NZ - Nuova Zelanda 7
SK - Slovacchia (Repubblica Slovacca) 7
BJ - Benin 6
BY - Bielorussia 6
LK - Sri Lanka 6
RS - Serbia 6
Totale 76.623
Città #
Ashburn 4.401
Fairfield 4.041
San Jose 2.781
Woodbridge 2.739
Singapore 2.391
Chandler 1.991
Houston 1.956
Milan 1.921
Wilmington 1.793
Seattle 1.749
Cambridge 1.423
Ann Arbor 1.369
Santa Clara 1.044
Vienna 1.008
Moscow 998
Jacksonville 870
Council Bluffs 786
The Dalles 725
Beijing 695
Hong Kong 672
Dearborn 616
Seoul 601
Boardman 596
Los Angeles 571
Hefei 492
Tokyo 472
Lawrence 465
Medford 453
Lauterbourg 434
Ho Chi Minh City 433
Dong Ket 425
Dublin 424
Ottawa 381
North Charleston 369
Dallas 311
Hanoi 307
Rome 260
New York 249
Helsinki 240
Des Moines 239
San Diego 233
Buffalo 200
Kent 191
São Paulo 185
London 176
Málaga 153
Frankfurt am Main 152
Kenitra 141
Taipei 129
Amman 126
Casablanca 125
Amsterdam 124
Shanghai 121
Orem 118
Brussels 111
Turin 111
Las Vegas 98
Chicago 95
Warsaw 94
Washington 91
Redwood City 80
Guangzhou 75
Montreal 71
Grafing 70
Naples 70
Haiphong 65
Da Nang 64
Rio de Janeiro 64
Belo Horizonte 61
Stockholm 61
Chennai 60
Norwalk 59
Atlanta 56
Columbus 52
Johannesburg 52
Phoenix 52
Redmond 52
Verona 52
Turku 50
Munich 48
Wuhan 48
Bologna 47
Denver 47
Brooklyn 46
Abidjan 45
Tianjin 45
Duncan 43
Frisco 42
Tashkent 40
Mumbai 39
Jakarta 38
Salt Lake City 38
Toronto 37
Brasília 35
Mountain View 35
Dhaka 34
Nuremberg 34
Ankara 33
Changsha 33
Florence 32
Totale 48.470
Nome #
High Scale-Factor Stability Frequency-Modulated MEMS Gyroscope: 3-Axis Sensor and Integrated Electronics Design 385
AM-to-PM conversion in varactor-tuned oscillators 309
A recombination- and trap-assisted tunneling model for stress-induced leakage current 308
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 306
A recombination model for transient and stationary stress-induced leakage current 301
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 297
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 294
Engineering grains of Ge2Sb2Te5 for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities 293
Characterization and Modeling of Current Transport in Metal/Ferroelectric/Semiconductor Tunnel Junctions 289
A 160 ua, 8 mdps/rt-Hz frequency-modulated MEMS yaw gyroscope 284
"Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM" 275
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 274
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 273
Power-jitter trade-off analysis in digital-to-time converters 272
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 269
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 267
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 264
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 261
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 256
Temperature Activation of the String Current and its Variability in 3-D NAND Flash Arrays 255
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 251
Reliability of NAND Flash memories: planar cells and emerging issues in 3D devices 250
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 248
A Monte Carlo investigation of nanocrystal memory reliability 247
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 242
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 241
Characterization and modeling of temperature effects in 3-D NAND Flash arrays - Part I: Polysilicon-induced variability 240
A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS 236
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 235
Reviewing the evolution of the NAND Flash technology 230
A 11-15 GHz CMOS ÷2 Frequency Divider For Broad-Band I/Q Generation 229
Assessment of threshold switching dynamics in phase-change chalcogenide memories 227
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 226
Optimization Metrics for Phase Change Memory (PCM) Cell Architectures 226
"Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation" 225
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector 224
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 224
The First Frequency-Modulated (FM) Pitch Gyroscope 224
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 223
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 223
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 221
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 221
Investigation of the turn-on of T-RAM cells under transient conditions 220
L' AMPLIFICATORE OPERAZIONALE. ESEMPI DI APPLICAZIONI CIRCUITALI 219
Impact of thermoelectric effects on phase change memory characteristics 219
A Multi-Channel Low-Power System-on-Chip for in Vivo Recording and Wireless Transmission of Neural Spikes 219
Investigation of the ISPP dynamics and of the programming efficiency of charge-trap memories 217
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning 216
A 64-Channel 965-μW Neural Recording SoC with UWB Wireless Transmission in 130-nm CMOS 215
A Step Ahead Toward a New Microscopic Picture for Charge Trapping/detrapping in Flash Memories 215
20 ps timing resolution with single-photon avalanche diodes 214
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 213
A Sub-400-nT/√Hz, 775-μW, Multi-Loop MEMS Magnetometer With Integrated Readout Electronics 213
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops 212
3D Monte Carlo simulation of the programming dynamics and their statistical variability in nanoscale charge-trap memories 212
2D QM simulation and optimization of decanano non-overlapped MOS devices 211
RTN effects in scaled Flash memory arrays 210
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 209
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 207
Bipolar-switching operated phase change memory (PCM) for improved high-temperature reliability 207
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking 207
Cell-to-Cell and Cycle-to-Cycle Retention Statistics in Phase-Change Memory Arrays 207
A reliable technique for experimental evaluation of crystallization activation energy in PCMs 206
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 206
Accuracy and issues of the spectroscopic analysis of RTN traps in nanoscale MOSFETs 206
Random telegraph noise-induced sensitivity of data retention to cell position in the programmed distribution of NAND Flash memory arrays 206
First detection of single-electron charging of the floating gate of NAND Flash memory cells 206
20 picosecond resolution single-photon solid-state detector 205
A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors 205
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique 204
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 204
A comparative study of characterization techniques for oxide reliability in Flash memories 204
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 204
Quantum--Corrected Drift--Diffusion Models for Transport in Semiconductor Devices 203
Random telegraph signal noise in phase change memory devices 203
A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS 202
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 201
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 201
Bipolar switching operation in phase change memory devices for high temperature retention 201
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 201
Analysis and optimization of a SAR ADC with Attenuation Capacitor 199
An integrated low-noise multichannel system for neural signals amplification 199
A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation. 199
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 198
Investigation of the Statistical Spread of the Time-Dependent Dielectric Breakdown in Polymeric Dielectrics for Galvanic Isolation 198
"A Multistandard Σ-Δ Fractional-N Frequency Synthesizer for 802.11a/b/g WLAN" 198
Accelerated reliability testing of Flash memory: accuracy and issues on a 45nm NOR technology 198
An efficient tool for the assisted design of SAR ADCs capacitive DACs 198
Impact of Temperature on the Amplitude of RTN Fluctuations in 3-D NAND Flash Cells 198
Fast-switching analog PLL with finite-impulse response 197
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 197
Fitting cells into a narrow VT interval: physical constraints along the lifetime of an extremely scaled NAND Flash memory array 196
A Wideband Fractional-N PLL with Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 196
Compact modeling of GIDL-assisted erase in 3-D NAND Flash strings 196
Random telegraph noise in 3d nand flash memories 196
"Electrical characterization of anomalous cells in phase change memory arrays" 195
An All-Digital Architecture for Low-Jitter Regulated Delay Lines 195
Characterization and modeling of temperature effects in 3-D NAND Flash arrays - Part II: Random telegraph noise 195
A Low-Noise Fractional-$N$ Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC 194
Defects spectroscopy in SiO2 by statistical random telegraph noise analysis 194
Totale 22.711
Categoria #
all - tutte 224.162
article - articoli 116.984
book - libri 1.356
conference - conferenze 103.038
curatela - curatele 412
other - altro 0
patent - brevetti 571
selected - selezionate 0
volume - volumi 1.801
Totale 448.324


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20224.647 180 626 373 229 536 183 311 266 304 254 490 895
2022/20234.904 570 319 152 508 569 664 55 397 830 297 443 100
2023/20242.283 124 495 168 199 143 245 138 118 38 256 38 321
2024/20258.204 92 166 250 207 1.330 570 390 916 1.479 438 1.214 1.152
2025/202632.099 5.254 5.357 1.320 2.442 1.518 1.578 5.143 1.631 1.702 2.906 1.018 2.230
2026/2027448 448 0 0 0 0 0 0 0 0 0 0 0
Totale 77.343