LACAITA, ANDREA LEONARDO
 Distribuzione geografica
Continente #
NA - Nord America 40.981
EU - Europa 20.739
AS - Asia 14.070
SA - Sud America 2.621
Continente sconosciuto - Info sul continente non disponibili 628
AF - Africa 601
OC - Oceania 40
Totale 79.680
Nazione #
US - Stati Uniti d'America 40.025
RU - Federazione Russa 6.839
IT - Italia 5.237
SG - Singapore 4.500
CN - Cina 3.576
BR - Brasile 2.206
VN - Vietnam 2.190
UA - Ucraina 1.427
DE - Germania 1.260
AT - Austria 1.039
SE - Svezia 893
FR - Francia 793
HK - Hong Kong 791
KR - Corea 782
GB - Regno Unito 745
FI - Finlandia 738
CA - Canada 661
JP - Giappone 588
NL - Olanda 454
IE - Irlanda 447
IN - India 358
MA - Marocco 291
ES - Italia 229
TW - Taiwan 212
BD - Bangladesh 192
BE - Belgio 149
AR - Argentina 135
PL - Polonia 134
JO - Giordania 128
MX - Messico 111
TR - Turchia 110
ZA - Sudafrica 91
IQ - Iraq 89
ID - Indonesia 78
EC - Ecuador 66
PK - Pakistan 60
PH - Filippine 54
CO - Colombia 53
CH - Svizzera 51
EG - Egitto 50
CI - Costa d'Avorio 46
CR - Costa Rica 45
VE - Venezuela 45
UZ - Uzbekistan 44
JM - Giamaica 40
SA - Arabia Saudita 40
IL - Israele 33
CL - Cile 31
AU - Australia 29
PY - Paraguay 29
AZ - Azerbaigian 28
CZ - Repubblica Ceca 28
RO - Romania 28
TH - Thailandia 27
PT - Portogallo 25
BG - Bulgaria 24
LT - Lituania 24
GR - Grecia 22
AE - Emirati Arabi Uniti 21
HU - Ungheria 21
PE - Perù 21
KE - Kenya 20
KZ - Kazakistan 20
TN - Tunisia 20
AL - Albania 19
IR - Iran 18
KG - Kirghizistan 17
DZ - Algeria 16
UY - Uruguay 16
BO - Bolivia 15
EU - Europa 15
NI - Nicaragua 14
NP - Nepal 14
DK - Danimarca 13
EE - Estonia 13
LV - Lettonia 13
PA - Panama 13
TT - Trinidad e Tobago 13
LB - Libano 12
ET - Etiopia 11
SI - Slovenia 11
SV - El Salvador 11
GT - Guatemala 10
LA - Repubblica Popolare Democratica del Laos 10
HN - Honduras 9
HR - Croazia 9
MD - Moldavia 9
MO - Macao, regione amministrativa speciale della Cina 9
DO - Repubblica Dominicana 8
MY - Malesia 8
NZ - Nuova Zelanda 8
OM - Oman 8
SN - Senegal 8
GE - Georgia 7
MK - Macedonia 7
MU - Mauritius 7
NO - Norvegia 7
SK - Slovacchia (Repubblica Slovacca) 7
BJ - Benin 6
BY - Bielorussia 6
Totale 78.940
Città #
Ashburn 4.556
Fairfield 4.041
San Jose 2.881
Woodbridge 2.740
Singapore 2.401
Milan 2.011
Chandler 1.991
Houston 1.962
Wilmington 1.794
Seattle 1.752
Cambridge 1.423
Ann Arbor 1.369
Council Bluffs 1.193
Santa Clara 1.090
Vienna 1.008
Moscow 998
Jacksonville 870
The Dalles 725
Beijing 702
Hong Kong 674
Dearborn 616
Los Angeles 602
Seoul 601
Boardman 597
Hefei 492
Tokyo 482
Lawrence 465
Medford 453
Ho Chi Minh City 435
Lauterbourg 434
Dong Ket 425
Dublin 424
Ottawa 382
North Charleston 370
Dallas 326
Hanoi 307
Rome 271
New York 259
Des Moines 241
Helsinki 240
San Diego 233
Buffalo 206
Kent 191
São Paulo 186
London 179
Phoenix 173
Málaga 153
Frankfurt am Main 152
Kenitra 141
Taipei 132
Shanghai 130
Amman 126
Amsterdam 126
Casablanca 125
Orem 119
Chicago 116
Brussels 111
Turin 111
Washington 104
Las Vegas 101
Warsaw 94
Redwood City 80
Naples 78
Guangzhou 75
Montreal 75
Atlanta 73
Grafing 70
Haiphong 65
Rio de Janeiro 65
Da Nang 64
Stockholm 62
Belo Horizonte 61
Chennai 61
Norwalk 59
Frisco 54
Columbus 53
Redmond 53
Verona 53
Johannesburg 52
Denver 51
Brooklyn 50
Turku 50
Bologna 49
Munich 48
Wuhan 48
Abidjan 45
Tianjin 45
San Francisco 44
Duncan 43
Toronto 42
Mumbai 40
Salt Lake City 40
Tashkent 40
Brasília 38
Jakarta 38
Newark 37
Miami 36
San José 36
Mountain View 35
Ankara 34
Totale 49.654
Nome #
High Scale-Factor Stability Frequency-Modulated MEMS Gyroscope: 3-Axis Sensor and Integrated Electronics Design 388
A comparative study of characterization techniques for oxide reliability in Flash memories 387
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters 372
A recombination- and trap-assisted tunneling model for stress-induced leakage current 339
"Geometry and material optimization for programming current scaling in phase-change memory" 338
A recombination model for transient and stationary stress-induced leakage current 331
AM-to-PM conversion in varactor-tuned oscillators 318
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 311
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 303
Engineering grains of Ge2Sb2Te5 for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities 303
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 300
Characterization and Modeling of Current Transport in Metal/Ferroelectric/Semiconductor Tunnel Junctions 293
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 291
A 160 ua, 8 mdps/rt-Hz frequency-modulated MEMS yaw gyroscope 289
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 283
A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC 281
"Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM" 279
Power-jitter trade-off analysis in digital-to-time converters 274
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 274
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 272
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 263
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 263
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 262
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 257
Temperature Activation of the String Current and its Variability in 3-D NAND Flash Arrays 257
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 253
Reliability of NAND Flash memories: planar cells and emerging issues in 3D devices 253
A Monte Carlo investigation of nanocrystal memory reliability 250
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 246
Characterization and modeling of temperature effects in 3-D NAND Flash arrays - Part I: Polysilicon-induced variability 243
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 242
A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS 240
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 238
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning 233
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 233
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 233
L' AMPLIFICATORE OPERAZIONALE. ESEMPI DI APPLICAZIONI CIRCUITALI 233
A 11-15 GHz CMOS ÷2 Frequency Divider For Broad-Band I/Q Generation 233
Reviewing the evolution of the NAND Flash technology 232
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 231
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector 229
Optimization Metrics for Phase Change Memory (PCM) Cell Architectures 229
Assessment of threshold switching dynamics in phase-change chalcogenide memories 229
"Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation" 228
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 228
A 2.9-to-4.0GHz fractional-N digital PLL with Bang-Bang phase detector and 560fsrms integrated jitter at 4.5mw power 228
A 64-Channel 965-μW Neural Recording SoC with UWB Wireless Transmission in 130-nm CMOS 225
The First Frequency-Modulated (FM) Pitch Gyroscope 225
A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS 224
Investigation of the turn-on of T-RAM cells under transient conditions 223
Impact of thermoelectric effects on phase change memory characteristics 221
Investigation of the ISPP dynamics and of the programming efficiency of charge-trap memories 220
A Multi-Channel Low-Power System-on-Chip for in Vivo Recording and Wireless Transmission of Neural Spikes 220
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 219
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique 218
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 218
20 ps timing resolution with single-photon avalanche diodes 218
A Step Ahead Toward a New Microscopic Picture for Charge Trapping/detrapping in Flash Memories 218
A Sub-400-nT/√Hz, 775-μW, Multi-Loop MEMS Magnetometer With Integrated Readout Electronics 217
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 216
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration 214
3D Monte Carlo simulation of the programming dynamics and their statistical variability in nanoscale charge-trap memories 214
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 213
RTN effects in scaled Flash memory arrays 213
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops 213
2D QM simulation and optimization of decanano non-overlapped MOS devices 213
A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors 212
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 212
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs 211
20 picosecond resolution single-photon solid-state detector 211
Bipolar-switching operated phase change memory (PCM) for improved high-temperature reliability 211
First detection of single-electron charging of the floating gate of NAND Flash memory cells 211
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 210
Random telegraph noise-induced sensitivity of data retention to cell position in the programmed distribution of NAND Flash memory arrays 210
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 210
Cell-to-Cell and Cycle-to-Cycle Retention Statistics in Phase-Change Memory Arrays 210
A reliable technique for experimental evaluation of crystallization activation energy in PCMs 209
Quantum--Corrected Drift--Diffusion Models for Transport in Semiconductor Devices 209
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking 209
Accuracy and issues of the spectroscopic analysis of RTN traps in nanoscale MOSFETs 208
Bipolar switching operation in phase change memory devices for high temperature retention 207
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion 206
Random telegraph signal noise in phase change memory devices 206
Analysis and optimization of a SAR ADC with Attenuation Capacitor 205
A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation. 205
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 203
Investigation of the Statistical Spread of the Time-Dependent Dielectric Breakdown in Polymeric Dielectrics for Galvanic Isolation 203
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 203
A Low-Noise Fractional-$N$ Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC 202
Fast-switching analog PLL with finite-impulse response 201
"Electrical characterization of anomalous cells in phase change memory arrays" 201
"A Multistandard Σ-Δ Fractional-N Frequency Synthesizer for 802.11a/b/g WLAN" 201
An efficient tool for the assisted design of SAR ADCs capacitive DACs 201
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 201
Impact of Temperature on the Amplitude of RTN Fluctuations in 3-D NAND Flash Cells 201
An integrated low-noise multichannel system for neural signals amplification 200
Accelerated reliability testing of Flash memory: accuracy and issues on a 45nm NOR technology 200
Fitting cells into a narrow VT interval: physical constraints along the lifetime of an extremely scaled NAND Flash memory array 200
Temperature acceleration of structural relaxation in amorphous Ge2Sb2Te2 199
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC 198
Totale 23.840
Categoria #
all - tutte 233.787
article - articoli 121.709
book - libri 1.427
conference - conferenze 107.758
curatela - curatele 423
other - altro 0
patent - brevetti 598
selected - selezionate 0
volume - volumi 1.872
Totale 467.574


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20223.841 0 0 373 229 536 183 311 266 304 254 490 895
2022/20234.904 570 319 152 508 569 664 55 397 830 297 443 100
2023/20242.283 124 495 168 199 143 245 138 118 38 256 38 321
2024/20258.204 92 166 250 207 1.330 570 390 916 1.479 438 1.214 1.152
2025/202632.099 5.254 5.357 1.320 2.442 1.518 1.578 5.143 1.631 1.702 2.906 1.018 2.230
2026/20272.785 856 1.495 434 0 0 0 0 0 0 0 0 0
Totale 79.680