This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successiveapproximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most powerefficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and nonidealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well.

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

BRENNA, STEFANO;BONFANTI, ANDREA GIOVANNI;LACAITA, ANDREA LEONARDO
2015-01-01

Abstract

This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successiveapproximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most powerefficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and nonidealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well.
2015
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015
978-1-4673-6576-5
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/972603
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