| Nome |
# |
|
An efficient tool for the assisted design of SAR ADCs capacitive DACs, file e0c31c08-e380-4599-e053-1705fe0aef77
|
1.608
|
|
High Scale-Factor Stability Frequency-Modulated MEMS Gyroscope: 3-Axis Sensor and Integrated Electronics Design, file e0c31c0b-d680-4599-e053-1705fe0aef77
|
812
|
|
A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS, file e0c31c11-11b3-4599-e053-1705fe0aef77
|
555
|
|
Reliability of NAND Flash memories: planar cells and emerging issues in 3D devices, file e0c31c0a-9dd0-4599-e053-1705fe0aef77
|
493
|
|
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop, file e0c31c0e-47f7-4599-e053-1705fe0aef77
|
386
|
|
Revisiting charge trapping/detrapping in Flash memories from a discrete and statistical standpoint - Part II: on-field operation and distributed-cycling effects, file e0c31c0d-54cc-4599-e053-1705fe0aef77
|
361
|
|
A 11-15 GHz CMOS /2 Frequency Divider For Broad-Band I/Q Generation, file e0c31c09-7fef-4599-e053-1705fe0aef77
|
342
|
|
A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors, file e0c31c0d-cb21-4599-e053-1705fe0aef77
|
332
|
|
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters, file e0c31c08-e580-4599-e053-1705fe0aef77
|
291
|
|
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking, file e0c31c0c-9156-4599-e053-1705fe0aef77
|
193
|
|
Random telegraph noise in 3d nand flash memories, file e0c31c11-75f4-4599-e053-1705fe0aef77
|
173
|
|
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators, file e0c31c11-b1dc-4599-e053-1705fe0aef77
|
167
|
|
A 11-15 GHz CMOS ÷2 Frequency Divider For Broad-Band I/Q Generation, file e0c31c0a-3f60-4599-e053-1705fe0aef77
|
156
|
|
Electrical Conductivity Discontinuity at Melt in Phase Change Memory, file e0c31c0d-c6c1-4599-e053-1705fe0aef77
|
152
|
|
Bipolar switching in chalcogenide phase change memory, file e0c31c0a-f263-4599-e053-1705fe0aef77
|
130
|
|
Random telegraph noise-induced sensitivity of data retention to cell position in the programmed distribution of NAND Flash memory arrays, file e0c31c0e-80bc-4599-e053-1705fe0aef77
|
130
|
|
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity, file e0c31c12-27be-4599-e053-1705fe0aef77
|
123
|
|
A Sub-400-nT/√Hz, 775-μW, Multi-Loop MEMS Magnetometer With Integrated Readout Electronics, file e0c31c0e-35d3-4599-e053-1705fe0aef77
|
116
|
|
Revisiting charge trapping/detrapping in Flash memories from a discrete and statistical standpoint - Part I: VT instabilities, file e0c31c0d-54cb-4599-e053-1705fe0aef77
|
114
|
|
Impact of thermoelectric effects on phase change memory characteristics, file e0c31c0e-501e-4599-e053-1705fe0aef77
|
114
|
|
Fitting cells into a narrow VT interval: physical constraints along the lifetime of an extremely scaled NAND Flash memory array, file e0c31c0e-75f0-4599-e053-1705fe0aef77
|
101
|
|
Cell-to-Cell and Cycle-to-Cycle Retention Statistics in Phase-Change Memory Arrays, file e0c31c0e-51c0-4599-e053-1705fe0aef77
|
91
|
|
First detection of single-electron charging of the floating gate of NAND Flash memory cells, file e0c31c0e-7785-4599-e053-1705fe0aef77
|
75
|
|
Modeling of dynamic operation of T-RAM cells, file e0c31c0e-7783-4599-e053-1705fe0aef77
|
71
|
|
Working principles of a DRAM cell based on gated-thyristor bistability, file e0c31c0d-c6bc-4599-e053-1705fe0aef77
|
70
|
|
Investigation of the turn-on of T-RAM cells under transient conditions, file e0c31c0e-b370-4599-e053-1705fe0aef77
|
39
|
|
High Quality Wafer-scale CVD Graphene on Molybdenum Thin Film for Sensing Application, file e0c31c08-26e3-4599-e053-1705fe0aef77
|
35
|
|
Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories, file e0c31c0e-7784-4599-e053-1705fe0aef77
|
31
|
|
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators, file e0c31c11-b1db-4599-e053-1705fe0aef77
|
17
|
|
Characterization and modeling of temperature effects in 3-D NAND Flash arrays - Part I: Polysilicon-induced variability, file e0c31c0c-4792-4599-e053-1705fe0aef77
|
8
|
|
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping, file e0c31c11-bdec-4599-e053-1705fe0aef77
|
8
|
|
The race of phase change memories to nanoscale storage and applications, file e0c31c08-15ad-4599-e053-1705fe0aef77
|
7
|
|
Electrical Conductivity Discontinuity at Melt in Phase Change Memory, file e0c31c08-2419-4599-e053-1705fe0aef77
|
7
|
|
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops, file e0c31c0b-a254-4599-e053-1705fe0aef77
|
7
|
|
A Background Calibration Technique to Control the Bandwidth of Digital PLLs, file e0c31c0c-6b87-4599-e053-1705fe0aef77
|
6
|
|
Single photon timing at picosecond resolution with silicon detectors, file e0c31c07-c55a-4599-e053-1705fe0aef77
|
5
|
|
A Sub-400-nT/√Hz, 775-μW, Multi-Loop MEMS Magnetometer With Integrated Readout Electronics, file e0c31c08-d803-4599-e053-1705fe0aef77
|
5
|
|
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop, file e0c31c08-feeb-4599-e053-1705fe0aef77
|
5
|
|
A Step Ahead Toward a New Microscopic Picture for Charge Trapping/detrapping in Flash Memories, file e0c31c09-7ec8-4599-e053-1705fe0aef77
|
5
|
|
Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution, file e0c31c09-8d15-4599-e053-1705fe0aef77
|
5
|
|
An Efficient Tool For Extraction of Interconnect Models in Submicron Layouts, file e0c31c0f-4845-4599-e053-1705fe0aef77
|
5
|
|
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter, file e0c31c0f-e17e-4599-e053-1705fe0aef77
|
5
|
|
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter, file e0c31c11-f3b5-4599-e053-1705fe0aef77
|
5
|
|
Investigation of the Statistical Spread of the Time-Dependent Dielectric Breakdown in Polymeric Dielectrics for Galvanic Isolation, file 076dcee1-ec52-41ee-828b-425ebe533a40
|
4
|
|
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time, file db11cd2e-cd55-4290-9394-880935980067
|
4
|
|
Resistance-dependent switching in NiO-based filamentary RRAM devices, file e0c31c07-e51f-4599-e053-1705fe0aef77
|
4
|
|
Revisiting charge trapping/detrapping in Flash memories from a discrete and statistical standpoint - Part I: VT instabilities, file e0c31c08-1ddf-4599-e053-1705fe0aef77
|
4
|
|
A Varactor Configuration Minimizing Flicker Noise Up-conversion in VCOs, file e0c31c08-2f1c-4599-e053-1705fe0aef77
|
4
|
|
An integrated low-noise multichannel system for neural signals amplification, file e0c31c08-3470-4599-e053-1705fe0aef77
|
4
|
|
Fully 2D quantum-mechanical simulation of nanoscale MOSFETs, file e0c31c08-3473-4599-e053-1705fe0aef77
|
4
|
|
Random telegraph noise-induced sensitivity of data retention to cell position in the programmed distribution of NAND Flash memory arrays, file e0c31c08-63ee-4599-e053-1705fe0aef77
|
4
|
|
Ultrafast Single Photon Avalanche Diodes without slow tails in the pulse response, file e0c31c08-ff7c-4599-e053-1705fe0aef77
|
4
|
|
Fully Integrated Systems for Neural Signal Recording: Technology Perspective and Low-Noise Front-End Design, file e0c31c09-c46b-4599-e053-1705fe0aef77
|
4
|
|
Impact of Temperature on the Amplitude of RTN Fluctuations in 3-D NAND Flash Cells, file e0c31c0b-5c86-4599-e053-1705fe0aef77
|
4
|
|
Bipolar switching operation in phase change memory devices for high temperature retention, file e0c31c0b-7009-4599-e053-1705fe0aef77
|
4
|
|
Investigation and Compact Modeling of the Time Dynamics of the GIDL-Assisted Increase of the String Potential in 3-D NAND Flash Arrays, file e0c31c0c-0d03-4599-e053-1705fe0aef77
|
4
|
|
A Background Calibration Technique to Control the Bandwidth of Digital PLLs, file e0c31c0c-9543-4599-e053-1705fe0aef77
|
4
|
|
Compact modeling of GIDL-assisted erase in 3-D NAND Flash strings, file e0c31c0d-8b9d-4599-e053-1705fe0aef77
|
4
|
|
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power, file e0c31c0e-8012-4599-e053-1705fe0aef77
|
4
|
|
Variability Effects in Nanowire and Macaroni MOSFETs—Part II: Random Telegraph Noise, file e0c31c0f-4f88-4599-e053-1705fe0aef77
|
4
|
|
Variability Effects in Nanowire and Macaroni MOSFETs—Part I: Random Dopant Fluctuations, file e0c31c0f-899f-4599-e053-1705fe0aef77
|
4
|
|
Characterization and Modeling of Current Transport in Metal/Ferroelectric/Semiconductor Tunnel Junctions, file e0c31c0f-ca1f-4599-e053-1705fe0aef77
|
4
|
|
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays, file e0c31c10-a067-4599-e053-1705fe0aef77
|
4
|
|
High-Density Solid-State Storage: A Long Path to Success, file e0c31c10-f15b-4599-e053-1705fe0aef77
|
4
|
|
A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies, file e0c31c11-1bac-4599-e053-1705fe0aef77
|
4
|
|
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS, file e0c31c11-979a-4599-e053-1705fe0aef77
|
4
|
|
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology, file e0c31c11-fda6-4599-e053-1705fe0aef77
|
4
|
|
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter, file e0c31c12-7d9f-4599-e053-1705fe0aef77
|
4
|
|
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise, file e0c31c12-991b-4599-e053-1705fe0aef77
|
4
|
|
Optimization Metrics for Phase Change Memory (PCM) Cell Architectures, file e0c31c07-bdf5-4599-e053-1705fe0aef77
|
3
|
|
Working principles of a DRAM cell based on gated-thyristor bistability, file e0c31c08-1c28-4599-e053-1705fe0aef77
|
3
|
|
A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors, file e0c31c08-1c42-4599-e053-1705fe0aef77
|
3
|
|
Revisiting charge trapping/detrapping in Flash memories from a discrete and statistical standpoint - Part II: on-field operation and distributed-cycling effects, file e0c31c08-1de0-4599-e053-1705fe0aef77
|
3
|
|
Investigation of the turn-on of T-RAM cells under transient conditions, file e0c31c08-248b-4599-e053-1705fe0aef77
|
3
|
|
A LOW-NOISE SUB-500uW LORENTZ FORCE BASED INTEGRATED MAGNETIC FIELD SENSING SYSTEM, file e0c31c08-2504-4599-e053-1705fe0aef77
|
3
|
|
A 2-GHz Differentially-Tuned VCO with Reduced Flicker Noise Up-Conversion, file e0c31c08-2db5-4599-e053-1705fe0aef77
|
3
|
|
Modeling of dynamic operation of T-RAM cells, file e0c31c08-3279-4599-e053-1705fe0aef77
|
3
|
|
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic, file e0c31c08-3ec8-4599-e053-1705fe0aef77
|
3
|
|
Size-dependent temperature instability in NiO–based resistive switching memory, file e0c31c08-4385-4599-e053-1705fe0aef77
|
3
|
|
Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories, file e0c31c08-5e4d-4599-e053-1705fe0aef77
|
3
|
|
Universal Thermoelectric Characteristic in Phase Change Memories, file e0c31c09-5efd-4599-e053-1705fe0aef77
|
3
|
|
Cell-to-Cell and Cycle-to-Cycle Retention Statistics in Phase-Change Memory Arrays, file e0c31c09-643e-4599-e053-1705fe0aef77
|
3
|
|
Emerging constraints on NAND Flash memory reliability, file e0c31c09-c9de-4599-e053-1705fe0aef77
|
3
|
|
Kinetic of resistance drift in PCM by structural relaxation of the amorphous chalcogenide phase, file e0c31c09-d862-4599-e053-1705fe0aef77
|
3
|
|
Progress of Phase Change Non Volatile Memory Devices, file e0c31c09-da2f-4599-e053-1705fe0aef77
|
3
|
|
A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS, file e0c31c0a-3b80-4599-e053-1705fe0aef77
|
3
|
|
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking, file e0c31c0f-24eb-4599-e053-1705fe0aef77
|
3
|
|
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking, file e0c31c0f-e180-4599-e053-1705fe0aef77
|
3
|
|
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking, file e0c31c10-007c-4599-e053-1705fe0aef77
|
3
|
|
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking, file e0c31c10-bae6-4599-e053-1705fe0aef77
|
3
|
|
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology, file 4523210a-27a0-421c-af9b-f29342b35708
|
2
|
|
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering, file 45fbfbe8-b126-4d65-8a02-d11dbd80de63
|
2
|
|
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, file dc36e857-1ff2-4898-8361-0b0ee66b3f1f
|
2
|
|
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion, file e0c31c07-ce7a-4599-e053-1705fe0aef77
|
2
|
|
Quantum--Corrected Drift--Diffusion Models for Transport in Semiconductor Devices, file e0c31c07-d50c-4599-e053-1705fe0aef77
|
2
|
|
Modeling of programming and read performance in phase-change memories - Part I: cell optimization and scaling, file e0c31c07-d68f-4599-e053-1705fe0aef77
|
2
|
|
Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials, file e0c31c07-db87-4599-e053-1705fe0aef77
|
2
|
|
A Wideband 3.6 GHz Digital Delta-Sigma Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation, file e0c31c07-e282-4599-e053-1705fe0aef77
|
2
|
|
A Multi-Channel Low-Power System-on-Chip for in vivo NeuralSpike Recording, file e0c31c07-e3e1-4599-e053-1705fe0aef77
|
2
|
|
TRADE-OFF BETWEEN DATA RETENTION AND RESET IN NIO RRAMS, file e0c31c07-e519-4599-e053-1705fe0aef77
|
2
|
| Totale |
7.548 |