In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time ΔΣ ADCs can’t be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7 dB, an SFDR of 81.8 dB, an ENoB of 11.45 and a power consumption of 43.4μW, corresponding to a figure-of-merit (FoM) of 155 fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70 dB.

A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS

BONFANTI, ANDREA GIOVANNI;LACAITA, ANDREA LEONARDO
2016

Abstract

In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time ΔΣ ADCs can’t be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7 dB, an SFDR of 81.8 dB, an ENoB of 11.45 and a power consumption of 43.4μW, corresponding to a figure-of-merit (FoM) of 155 fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70 dB.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1000257
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