RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

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Mostrati risultati da 151 a 185 di 185
Titolo Data di pubblicazione Autori File
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli, AlessioMercandelli, MarioLacaita, Andrea L.Samori, CarloLevantino, Salvatore
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 1-gen-2019 Santiccioli, AlessioSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 1-gen-2020 Mercandelli, MarioBertulessi, LucaSanticcioli, AlessioSamori, CarloLevantino, Salvatore +
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Santiccioli A.Mercandelli M.Bertulessi L.Parisi A.Lacaita A. L.Samori C.Levantino S. +
Jitter Minimization in Digital PLLs with Mid-Rise TDCs 1-gen-2020 Karman S.Samori C.Levantino S. +
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
Bang-bang digital PLLs for wireless systems 1-gen-2020 S. Levantinoc. Samori
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 1-gen-2020 Mercandelli M.Santiccioli A.Parisi A.Bertulessi L.Lacaita A. L.Samori C.Levantino S. +
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability 1-gen-2021 Karman S.Tesolin F.Dago A.Mercandelli M.Samori C.Levantino S.
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends 1-gen-2021 Karman S.Levantino S.Mazzanti A.Samori C.Tesolin F. +
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 1-gen-2021 Angelo ParisiMario MercandelliCarlo SamoriAndrea Leonardo Lacaita
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs 1-gen-2021 Mercandelli M.Levantino S.Samori C. +
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 1-gen-2021 Mercandelli, MarioBertulessi, LucaSamori, CarloLevantino, Salvatore
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
Digital PLLs: The modern timing reference for radar and communication systems 1-gen-2021 C. SamoriL. Bertulessi
A Novel Topology of Coupled Phase-Locked Loops 1-gen-2021 Karman, SalehTesolin, FrancescoLevantino, SalvatoreSamori, Carlo
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 1-gen-2022 Dartizio S. M.Buccoleri F.Tesolin F.Bertulessi L.Bevilacqua A.Samori C.Lacaita A. L.Levantino S. +
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 1-gen-2022 Buccoleri F.Dartizio S. M.Tesolin F.Santiccioli A.Bevilacqua A.Bertulessi L.Cherniak D.Samori C.Lacaita A. L.Levantino S. +
A Digital PLL with Multi-tap LMS-based Bandwidth Control 1-gen-2022 Bertulessi, LucaSamori, CarloLevantino, Salvatore +
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 1-gen-2022 Simone M. DartizioFrancesco BuccoleriFrancesco TesolinAlessio SanticcioliDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore Levantino +
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2022 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 1-gen-2022 Be' G.Bertulessi L.Ricci L.Scaletti L.Mercandelli M.Lacaita A. L.Levantino S.Samori C.Bonfanti A. +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
Concurrent effect of redundancy and switching algorithms in SAR ADCs 1-gen-2022 Ricci, LucaScaletti, LorenzoBe, GabrieleBertulessi, LucaLevantino, SalvatoreSamori, CarloBonfanti, Andrea
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 1-gen-2022 Bertulessi, LucaMercandelli, MarioSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 1-gen-2022 Lorenzo ScalettiGabriele BeAngelo ParisiLuca BertulessiLuca RicciMario MercandelliSalvatore LevantinoCarlo SamoriAndrea Bonfanti
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 1-gen-2023 L. RicciL. ScalettiG. Be'M. RoccoL. BertulessiS. LevantinoA. LacaitaC. SamoriA. Bonfanti
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, SMTesolin, FCastoro, GBuccoleri, FRossoni, MCherniak, DSamori, CLacaita, ALLevantino, S
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2023 Tesolin, FrancescoDartizio, Simone M.Buccoleri, FrancescoSanticcioli, AlessioBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization 1-gen-2024 Gabriele ZanolettiLorenzo ScalettiGabriele BeLuca RicciMichele RoccoLuca BertulessiCarlo SamoriAndrea Bonfanti
Mostrati risultati da 151 a 185 di 185
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