This work presents a novel architecture of frequency synthesizer which allows to easily couple two digital PLLs (synchronized to the same reference source) and scale phase noise and power consumption. The second-harmonic component of the two digital oscillators are inductively extracted and power-combined on-chip. A digital correction loop guarantees phase alignment of the two PLLs even in the presence of mismatch. The frequency synthesizer spans from 18.8 to 22.3GHz, the phase noise at 1MHz offset scales from -113 to -116dBc/Hz and power consumption from 18.5 to 37.1mW, by activating one or two cores, respectively.

A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability

Karman S.;Tesolin F.;Dago A.;Mercandelli M.;Samori C.;Levantino S.
2021

Abstract

This work presents a novel architecture of frequency synthesizer which allows to easily couple two digital PLLs (synchronized to the same reference source) and scale phase noise and power consumption. The second-harmonic component of the two digital oscillators are inductively extracted and power-combined on-chip. A digital correction loop guarantees phase alignment of the two PLLs even in the presence of mismatch. The frequency synthesizer spans from 18.8 to 22.3GHz, the phase noise at 1MHz offset scales from -113 to -116dBc/Hz and power consumption from 18.5 to 37.1mW, by activating one or two cores, respectively.
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
978-1-6654-2549-0
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1183865
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