BUCCOLERI, FRANCESCO

BUCCOLERI, FRANCESCO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Titolo Data di pubblicazione Autori File
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 1-gen-2022 Dartizio S. M.Buccoleri F.Tesolin F.Bertulessi L.Bevilacqua A.Samori C.Lacaita A. L.Levantino S. +
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 1-gen-2022 Buccoleri F.Dartizio S. M.Tesolin F.Santiccioli A.Bevilacqua A.Bertulessi L.Cherniak D.Samori C.Lacaita A. L.Levantino S. +
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 1-gen-2022 Simone M. DartizioFrancesco BuccoleriFrancesco TesolinAlessio SanticcioliDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore Levantino +
A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies 1-gen-2021 Francesco BuccoleriAndrea Leonardo LacaitaAndrea Giovanni Bonfanti
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, SMTesolin, FCastoro, GBuccoleri, FRossoni, MCherniak, DSamori, CLacaita, ALLevantino, S
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2023 Tesolin, FrancescoDartizio, Simone M.Buccoleri, FrancescoSanticcioli, AlessioBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore