MERCANDELLI, MARIO

MERCANDELLI, MARIO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 21 (tempo di esecuzione: 0.028 secondi).
Titolo Data di pubblicazione Autori File
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli, AlessioMercandelli, MarioLacaita, Andrea L.Samori, CarloLevantino, Salvatore
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli A.Mercandelli M.Lacaita A. L.Samori C.Levantino S.
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 1-gen-2022 Lorenzo ScalettiGabriele BeAngelo ParisiLuca BertulessiLuca RicciMario MercandelliSalvatore LevantinoCarlo SamoriAndrea Bonfanti
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2021 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 1-gen-2020 Mercandelli M.Santiccioli A.Parisi A.Bertulessi L.Lacaita A. L.Samori C.Levantino S. +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2021 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability 1-gen-2021 Karman S.Tesolin F.Dago A.Mercandelli M.Samori C.Levantino S.
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 1-gen-2020 Mercandelli, MarioBertulessi, LucaSanticcioli, AlessioSamori, CarloLevantino, Salvatore +
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 1-gen-2021 Mercandelli, MarioBertulessi, LucaSamori, CarloLevantino, Salvatore
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Santiccioli A.Mercandelli M.Bertulessi L.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 1-gen-2022 Be' G.Bertulessi L.Ricci L.Scaletti L.Mercandelli M.Lacaita A. L.Levantino S.Samori C.Bonfanti A. +
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 1-gen-2018 MERCANDELLI, MARIOLuigi GrimaldiLuca BertulessiCarlo SamoriAndrea L. LacaitaSalvatore Levantino
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs 1-gen-2021 Mercandelli M.Levantino S.Samori C. +
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 1-gen-2022 Bertulessi, LucaMercandelli, MarioSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 1-gen-2021 Angelo ParisiMario MercandelliCarlo SamoriAndrea Leonardo Lacaita
RADAR SIGNAL MODULATOR WITH BANDWIDTH COMPENSATION AND FREQUENCY OFFSET SEQUENCE 1-gen-2019 S. LevantinoM. Mercandelli +
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 1-gen-2021 Parisi, A.Tesolin, F.Mercandelli, M.Bertulessi, L.Lacaita, A. L.