KARMAN, SALEH

KARMAN, SALEH  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 9 di 9 (tempo di esecuzione: 0.015 secondi).
Titolo Data di pubblicazione Autori File
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2021 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 1-gen-2019 Grimaldi, LuigiBertulessi, LucaKarman, SalehSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability 1-gen-2021 Karman S.Tesolin F.Dago A.Mercandelli M.Samori C.Levantino S.
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Jitter Minimization in Digital PLLs with Mid-Rise TDCs 1-gen-2020 Karman S.Samori C.Levantino S. +
A Novel Topology of Coupled Phase-Locked Loops 1-gen-2021 Karman, SalehTesolin, FrancescoLevantino, SalvatoreSamori, Carlo
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends 1-gen-2021 Karman S.Levantino S.Mazzanti A.Samori C.Tesolin F. +
Single-resonator, time-switched FM MEMS accelerometer with theoretical offset drift complete cancellation 1-gen-2018 Marra, Cristiano R.KARMAN, SALEHTocchio, AlessandroLangfelder, Giacomo +